llvm dev - Jan 2011 - [LLVMdev] Question about porting LLVM - code selection without assembler feature

Hello all,

I am adding a new target into LLVM. However there is a assembler for that
target and I just want LLVM to generate assembly. I read the document
"Writing an LLVM Backend". I am wondering to know whether I can ignore
the
Inst field in the following example:

class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instruction {

  field bits<32> Inst;
  let Namespace = "SP";
  bits<2> op;
  let Inst{31-30} = op;
  dag OutOperandList = outs;
  dag InOperandList = ins;
  let AsmString   = asmstr;
  let Pattern = pattern;
}

And define the instruction class of ported target as:

class Instxxx<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instruction {

  let Namespace = "xxx";
  dag OutOperandList = outs;
  dag InOperandList = ins;
  let AsmString   = asmstr;
  let Pattern = pattern;
}

Second, I have read the documentation of "TableGen Fundamentals" and
"The LLVM Target Independent Code Generator". But I don't know how
to
fill the dag filed of instruction. like [(store IntRegs:$src,
ADDRrr:$addr)] of the following example:

def STrr  : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),

               "st $src, [$addr]", [(store IntRegs:$src,
ADDRrr:$addr)]>;


Would anyone mind to tell me where to find the documentation of the
dag in Independent Code Generator??


thanks a lot


yi-hong
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Lu Mitnick <king19880326 at gmail.com> writes:
> Hello all,
>
> I am adding a new target into LLVM. However there is a assembler for
> that target and I just want LLVM to generate assembly. I read the
> document "Writing an LLVM Backend". I am wondering to know
whether I
> can ignore the Inst field in the following example:
I'm not an expert here so I'll defer to others.
> Second, I have read the documentation of "TableGen Fundamentals"
and
> "The LLVM Target Independent Code Generator". But I don't
know how to
> fill the dag filed of instruction. like [(store IntRegs:$src,
> ADDRrr:$addr)] of the following example:
>
> def STrr  : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
>
>                "st $src, [$addr]", [(store IntRegs:$src,
ADDRrr:$addr)]>;
>
> Would anyone mind to tell me where to find the documentation of the
> dag in Independent Code Generator??
Think of the DAG pattern as a LISP expression.  Each level of parens is
a subtree in the DAG, so

             +
            / \
           /   \
          a     *
               / \
              b   c

Becomes:

[(add REGCLASS:$a, (mul REGCLASS:&b, REGCLASS:$c))]

That's the pattern your codegen will match and turn into the asm string
you provide (The "st $src, [$addr]" in your example).

Does that help?

                               -Dave

On Jan 21, 2011, at 11:09 PM, Lu Mitnick wrote:
> I am adding a new target into LLVM. However there is a assembler for that
target and I just want LLVM to generate assembly. I read the document
"Writing an LLVM Backend". I am wondering to know whether I can ignore
the Inst field in the following example:
> 
> class InstSP<dag outs, dag ins, string asmstr, list<dag>
pattern> : Instruction {
>   field bits<32> Inst;
>   let Namespace = "SP";
>   bits<2> op;
>   let Inst{31-30} = op;       
>   dag OutOperandList = outs;
>   dag InOperandList = ins;
>   let AsmString   = asmstr;
>   let Pattern = pattern;
> }
> And define the instruction class of ported target as:
> class Instxxx<dag outs, dag ins, string asmstr, list<dag>
pattern> : Instruction {
>   let Namespace = "xxx";      
>   dag OutOperandList = outs;
>   dag InOperandList = ins;
>   let AsmString   = asmstr;
>   let Pattern = pattern;
> }
Hi Yi-Hong,

Yes, you may go ahead and omit the Inst field. That's used to represent the
instruction encoding.

-bw

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Hello David,

Thanks for your example. Is that means that DAG pattern is consist of LLVM
IR instruction?? I met an example  [(set CPURegs:$dst, (OpNode CPURegs:$b,
CPURegs:$c))] of MipsInstrInfo.td, but I can't find correspond LLVM IR
instruction of "set" in "LLVM Language Reference Manual". Is
that correspond
to $dst = op $b, $c?? Would you mind to tell me whether there is a reference
of all possible element of DAG??

thanks a lot

yi-hong

2011/1/25 David A. Greene <greened at obbligato.org>
> Lu Mitnick <king19880326 at gmail.com> writes:
>
> > Hello all,
> >
> > I am adding a new target into LLVM. However there is a assembler for
> > that target and I just want LLVM to generate assembly. I read the
> > document "Writing an LLVM Backend". I am wondering to know
whether I
> > can ignore the Inst field in the following example:
>
> I'm not an expert here so I'll defer to others.
>
> > Second, I have read the documentation of "TableGen
Fundamentals" and
> > "The LLVM Target Independent Code Generator". But I
don't know how to
> > fill the dag filed of instruction. like [(store IntRegs:$src,
> > ADDRrr:$addr)] of the following example:
> >
> > def STrr  : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr,
IntRegs:$src),
> >
> >                "st $src, [$addr]", [(store IntRegs:$src,
ADDRrr:$addr)]>;
> >
> > Would anyone mind to tell me where to find the documentation of the
> > dag in Independent Code Generator??
>
> Think of the DAG pattern as a LISP expression.  Each level of parens is
> a subtree in the DAG, so
>
>             +
>            / \
>           /   \
>          a     *
>               / \
>              b   c
>
> Becomes:
>
> [(add REGCLASS:$a, (mul REGCLASS:&b, REGCLASS:$c))]
>
> That's the pattern your codegen will match and turn into the asm string
> you provide (The "st $src, [$addr]" in your example).
>
> Does that help?
>
>                               -Dave
>
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