Displaying 11 results from an estimated 11 matches for "0b000100".
Did you mean:
00000100
2007 Dec 03
2
[LLVMdev] Using frameindex in a pattern
...I have a target that does not have register+constant
addressing mode. Then, I have DAG like:
(store ..., (frameindex))
Targets like SPARC have the following patterns to catch this:
def ADDRri : ComplexPattern<i32, 2,
"SelectADDRri", [frameindex], []>;
def STri : F3_2<3, 0b000100,
(outs), (ins MEMri:$addr, IntRegs:$src),
"st $src, [$addr]",
[(store IntRegs:$src, ADDRri:$addr)]>;
Where ADDRri will eventually turn into register+constant
addressing in assembler.
The IA64 target has explicit case in it's Sele...
2011 Jan 22
3
[LLVMdev] Question about porting LLVM - code selection without assembler feature
...tern;
}
Second, I have read the documentation of "TableGen Fundamentals" and
"The LLVM Target Independent Code Generator". But I don't know how to
fill the dag filed of instruction. like [(store IntRegs:$src,
ADDRrr:$addr)] of the following example:
def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>;
Would anyone mind to tell me where to find the documentation of the
dag in Independent Code Generator??
thanks a lot
yi-hong
-------------- next part -------------...
2011 Jan 24
0
[LLVMdev] Question about porting LLVM - code selection without assembler feature
...read the documentation of "TableGen Fundamentals" and
> "The LLVM Target Independent Code Generator". But I don't know how to
> fill the dag filed of instruction. like [(store IntRegs:$src,
> ADDRrr:$addr)] of the following example:
>
> def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
>
> "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>;
>
> Would anyone mind to tell me where to find the documentation of the
> dag in Independent Code Generator??
Think of the DAG pattern as a LISP expre...
2007 Dec 04
0
[LLVMdev] Using frameindex in a pattern
...er+constant
> addressing mode. Then, I have DAG like:
>
> (store ..., (frameindex))
>
> Targets like SPARC have the following patterns to catch this:
>
> def ADDRri : ComplexPattern<i32, 2,
> "SelectADDRri", [frameindex], []>;
> def STri : F3_2<3, 0b000100,
> (outs), (ins MEMri:$addr, IntRegs:$src),
> "st $src, [$addr]",
> [(store IntRegs:$src, ADDRri:$addr)]>;
>
> Where ADDRri will eventually turn into register+constant
> addressing in assembler.
>
> The IA64 target...
2007 Dec 04
1
[LLVMdev] Using frameindex in a pattern
...mode. Then, I have DAG like:
>>
>> (store ..., (frameindex))
>>
>> Targets like SPARC have the following patterns to catch this:
>>
>> def ADDRri : ComplexPattern<i32, 2,
>> "SelectADDRri", [frameindex], []>;
>> def STri : F3_2<3, 0b000100,
>> (outs), (ins MEMri:$addr, IntRegs:$src),
>> "st $src, [$addr]",
>> [(store IntRegs:$src, ADDRri:$addr)]>;
>>
>> Where ADDRri will eventually turn into register+constant
>> addressing in assembler.
&...
2011 Nov 08
0
[LLVMdev] Newbie Question: How are the values set in a Sparc store instruction (e.g. STri)?
I'm a bit confused as to how some of the values in a Sparc store
instruction actually come to be set. The Sparc backend defines a store as:
def STri : F3_2<3, 0b000100,
(outs), (ins MEMri:$addr, IntRegs:$src),
"st $src, [$addr]",
[(store IntRegs:$src, ADDRri:$addr)]>;
F3_2 and it's superclasses are defined as follows:
class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,...
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
...0, srl>;
defm SRA : F3_12<"sra" , 0b100111, sra>;
defm ADD : F3_12<"add" , 0b000000, add>;
defm ADDCC : F3_12<"addcc", 0b010000, addc>;
defm ADDX : F3_12<"addx" , 0b001000, adde>;
defm SUB : F3_12<"sub" , 0b000100, sub>;
defm SUBX : F3_12<"subx" , 0b001100, sube>;
defm SUBCC : F3_12<"subcc", 0b010100, SPcmpicc>;
...
Each of these 'defm's expand into two instructions.
> The semantic of such a description would mean that $dst should be one
> of GR8, GR16, G...
2011 Jan 24
1
[LLVMdev] Question about porting LLVM - code selection without assembler feature
..."TableGen Fundamentals" and
> > "The LLVM Target Independent Code Generator". But I don't know how to
> > fill the dag filed of instruction. like [(store IntRegs:$src,
> > ADDRrr:$addr)] of the following example:
> >
> > def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src),
> >
> > "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>;
> >
> > Would anyone mind to tell me where to find the documentation of the
> > dag in Independent Code Generator??
>
> Think...
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi,
I'm trying to implement a new backend for an embedded CISC processor.
Therefore I thought that it makes sense to take X86 target as a basis,
to save some time.
But when I look into the X86InstrInfo.td, I have a very strong feeling
that it is one of the most complex instruction set descriptions
compared to other targets. I can imagine that this is due to the
complexity of X86's
2014 Jun 07
3
[LLVMdev] Load/Store Instruction Error
Hi all,
I started to write an LLVM backend for custom CPU. I created XXXInstrInfo
but there are some problems. I searched for it but I couldn't find
anything. Can anyone help me?
include "XXXInstrFormats.td"
def simm16 : Operand<i32> {
let DecoderMethod = "DecodeSimm16";
}
def mem : Operand<i32> {
let PrintMethod = "printMemOperand";
let
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
...: F3_12<"sra" , 0b100111, sra>;
> defm ADD : F3_12<"add" , 0b000000, add>;
> defm ADDCC : F3_12<"addcc", 0b010000, addc>;
> defm ADDX : F3_12<"addx" , 0b001000, adde>;
> defm SUB : F3_12<"sub" , 0b000100, sub>;
> defm SUBX : F3_12<"subx" , 0b001100, sube>;
> defm SUBCC : F3_12<"subcc", 0b010100, SPcmpicc>;
> ...
>
> Each of these 'defm's expand into two instructions.
>
>> The semantic of such a description would mean that $dst...