search for: memrr

...-- lib/Target/PowerPC/PPCInstr64Bit.td (revision 52957) +++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy) @@ -116,23 +116,34 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst)>; -// Atomic operations. -def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tldarx $rD, $ptr", - [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>; +// Atomic operations +let usesCustomDAGSchedInserter = 1 in { + let Uses = [CR0] in { + def ATOMIC_LOAD_ADD_I64 : Pseudo&lt...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...-- lib/Target/PowerPC/PPCInstr64Bit.td (revision 53464) +++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy) @@ -116,23 +116,34 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst)>; -// Atomic operations. -def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tldarx $rD, $ptr", - [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>; +// Atomic operations +let usesCustomDAGSchedInserter = 1 in { + let Uses = [CR0] in { + def ATOMIC_LOAD_ADD_I64 : Pseudo&lt...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...-- lib/Target/PowerPC/PPCInstr64Bit.td (revision 52957) +++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy) @@ -116,23 +116,34 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst)>; -// Atomic operations. -def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tldarx $rD, $ptr", - [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>; +// Atomic operations +let usesCustomDAGSchedInserter = 1 in { + let Uses = [CR0] in { + def ATOMIC_LOAD_ADD_I64 : Pseudo&lt...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...-- lib/Target/PowerPC/PPCInstr64Bit.td (revision 52957) +++ lib/Target/PowerPC/PPCInstr64Bit.td (working copy) @@ -116,23 +116,35 @@ def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)), (BL8_ELF texternalsym:$dst)>; -// Atomic operations. -def LDARX : Pseudo<(outs G8RC:$rD), (ins memrr:$ptr, i32imm:$label), - "\nLa${label}_entry:\n\tldarx $rD, $ptr", - [(set G8RC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>; +// Atomic operations +let usesCustomDAGSchedInserter = 1 in { + let Uses = [CR0] in { + let Uses = [R0] in + def ATOMIC_...

...s, I can so far only use one memory with (for example) def LDr1 : F1< (outs GenRegs:$dst), (ins GenRegs:$addr), "ld*0* $dst, ($addr)", [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>; and def LDrr : F1< (outs GenRegs:$dst), (ins MEMrr:$addr), "ld*0* $dst, ($addr)", [(set GenRegs:$dst, (load ADDRrr:$addr))],IIGenLoad>; What i want to do is to be able to also have these two: def LDr1 : F1< (outs GenRegs:$dst), (ins GenRegs:$addr), "ld*1* $dst, ($addr)&...

Hello, My target has two data memories, each with its own load/store instructions but also has some instructions using both memories. I want to be able to access both memories in C-programs through the address space attribute. I have two ideas so far: Either: use two sets of addressing modes in InstrInfo.td: def ADDRrr_A : ComplexPattern<i16, 2, “SelectADDRrr_A", [], []>; def ADDRri :

Hi all, I'm trying to figure out how to add the instructions required for llvm.atomic.cmp.swap.i32 on PowerPC. I figured out LWARX (patch attached) but the other two (CMP_UNRESw and STWCX) require multiple instructions: let Defs = [CR0] in { def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label), "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:", [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>; def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:$label), &quo...

...read the documentation of "TableGen Fundamentals" and "The LLVM Target Independent Code Generator". But I don't know how to fill the dag filed of instruction. like [(store IntRegs:$src, ADDRrr:$addr)] of the following example: def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; Would anyone mind to tell me where to find the documentation of the dag in Independent Code Generator?? thanks a lot yi-hong -------------- next part -------------- An HTML attachment...

...of "TableGen Fundamentals" and > "The LLVM Target Independent Code Generator". But I don't know how to > fill the dag filed of instruction. like [(store IntRegs:$src, > ADDRrr:$addr)] of the following example: > > def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), > > "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; > > Would anyone mind to tell me where to find the documentation of the > dag in Independent Code Generator?? Think of the DAG pattern as a LISP expression. Each level o...

...does seem to manage schedules okay. Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though): // Memory address: 32-bit base register + 16-bit offset register def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>; def MEMrr : Operand<iPTR> { let PrintMethod = "printMemOffsetOperand"; let MIOperandInfo = (ops RC32, RC16_l); } but it is still happy to select for offset’s > 16-bits. There is something I am just not yet getting right, but it looks like I am on the right track. All the be...

...e documentation is still in date. Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though): // Memory address: 32-bit base register + 16-bit offset register def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>; def MEMrr : Operand<iPTR> { let PrintMethod = "printMemOffsetOperand"; let MIOperandInfo = (ops RC32, RC16_l); } but it is still happy to select for offset’s > 16-bits. There is something I am just not yet getting right, but it looks like I am on the right track. I believe...

...n? No, at the MI level, we can currently only encode that there is a constraint that some input operand must be the same as some output operand. For example, the PowerPC backend has a pre-increment store encoded like this: def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), "stdux $rS, $dst", LdStSTDU, []>, RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">; } def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), (STDUX $rS, $ptrreg, $ptroff)>; N...

...t the MI level, we can currently only encode that there is a constraint that some input operand must be the same as some output operand. For example, the PowerPC backend has a pre-increment store encoded like this: > > def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), > "stdux $rS, $dst", LdStSTDU, []>, > RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">; > } > > def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), > (STDU...