search for: addrrr

I have an operation which loads a 16 bit block of data as 2 8-bit elements, sign extends the both parts to 32 bits and stores the result into 64-bit vector register. How can I define the pattern for this? just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))] gives me error that extloav2i8 is not defined. (the same principle works for scalar sextload) So I need to define it from the SDNodes? But how? there is no SDNode for extload? it's load with some extra parameters?

...OperandList = ins; let AsmString = asmstr; let Pattern = pattern; } Second, I have read the documentation of "TableGen Fundamentals" and "The LLVM Target Independent Code Generator". But I don't know how to fill the dag filed of instruction. like [(store IntRegs:$src, ADDRrr:$addr)] of the following example: def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; Would anyone mind to tell me where to find the documentation of the dag in Independent Code Generat...

Hi Heikki, > just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))] > > gives me error that extloav2i8 is not defined. I don't have a target to test this on, but looking at include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8" PatFrag, at least. I'd suggest a pattern along the lines of: (set V2I32Regs:$result, (v...

On 10/30/2012 04:52 PM, Tim Northover wrote: > Hi Heikki, > >> just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))] >> >> gives me error that extloav2i8 is not defined. > > I don't have a target to test this on, but looking at > include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8" > PatFrag, at least. I'd suggest a pattern along the lines of:...

...gs:$addr), "ld*0* $dst, ($addr)", [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>; and def LDrr : F1< (outs GenRegs:$dst), (ins MEMrr:$addr), "ld*0* $dst, ($addr)", [(set GenRegs:$dst, (load ADDRrr:$addr))],IIGenLoad>; What i want to do is to be able to also have these two: def LDr1 : F1< (outs GenRegs:$dst), (ins GenRegs:$addr), "ld*1* $dst, ($addr)", [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>; and def LDrr : F1<...

...#39;m not an expert here so I'll defer to others. > Second, I have read the documentation of "TableGen Fundamentals" and > "The LLVM Target Independent Code Generator". But I don't know how to > fill the dag filed of instruction. like [(store IntRegs:$src, > ADDRrr:$addr)] of the following example: > > def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), > > "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; > > Would anyone mind to tell me where to find the documentation of the >...

...et has two data memories, each with its own load/store instructions but also has some instructions using both memories. I want to be able to access both memories in C-programs through the address space attribute. I have two ideas so far: Either: use two sets of addressing modes in InstrInfo.td: def ADDRrr_A : ComplexPattern<i16, 2, “SelectADDRrr_A", [], []>; def ADDRri : ComplexPattern<i16, 2, "SelectADDRri", [frameindex], []>; and def ADDRrr_B : ComplexPattern<i16, 2, "SelectADDRrr_B", [], []>; Or: do something in one of the lowering functions to catch lo...

Hi all, I started to write an LLVM backend for custom CPU. I created XXXInstrInfo but there are some problems. I searched for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let

...AllRegs:i32:$a - Complexity = 3 // Dst: (MVrr:i32 AllRegs:i32:$a) /*4334*/ /*Scope*/ 14, /*->4349*/ /*4335*/ OPC_CheckOpcode, TARGET_VAL(ISD::ADD), /*4338*/ OPC_RecordChild0, // #0 = $a /*4339*/ OPC_RecordChild1, // #1 = $b /*4340*/ OPC_MorphNodeTo, TARGET_VAL(MyTarget::ADDrrr), 0, Matching fails from the beginning because no pattern matches (that's correct) and it fails at index 4310 because ADD != MBPISD::RET_FLAG. Now, matching continues at index 4322 and the only check there is the typecheck MVT::i32 of the input. It doesn't check any opcodes! That means t...

...so I'll defer to others. > > > Second, I have read the documentation of "TableGen Fundamentals" and > > "The LLVM Target Independent Code Generator". But I don't know how to > > fill the dag filed of instruction. like [(store IntRegs:$src, > > ADDRrr:$addr)] of the following example: > > > > def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), > > > > "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; > > > > Would anyone mind to tell me where to find...

...ly a limitation for inferring an instruction from the patterns, because it does seem to manage schedules okay. Curiously, my memory Reg32+Reg16 pattern is very similar to yours (the 16-bit offset is sign-extended though): // Memory address: 32-bit base register + 16-bit offset register def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", []>; def MEMrr : Operand<iPTR> { let PrintMethod = "printMemOffsetOperand"; let MIOperandInfo = (ops RC32, RC16_l); } but it is still happy to select for offset’s > 16-bits. There is something I am just not ye...

Thanks again for your help Steve, I’m thinking perhaps my “SelectADDRrr” pattern is inadequate. The sign-extension is at the hardware level, the code generator sees (should see) it as a 16-bit signed register value. My implementation is just: bool SHAVEISelDAGtoDAG::SelectADDRrr(SDValue &Addr, SDValue &Base, SDValue &Offset) { if ((Addr.getOpcode()...

Hi Quentin, >> Yes, the dags in view-isel-dags and view-legalize-types-dags are correct (the add operations are here and are their results are used) and the dags are the same. > > And what about view-sched-dags? The DAG looks like I described below (*) > This one should give you what has been selected. So if this is not correct, you have indeed a problem in the selection

My target machine uses the same 64-bit registers for integers and floating point. Do I have to specify a different register class for floating point that uses the same set of registers? Is there a target which does this I can copy? thanks, brian

Jakob Stoklund Olesen wrote: > I have updated TableGen to support a new format for instruction selection patterns. > > Before: > > def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>; > > After: > > def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; > > Since the pattern matching happens on a DAG with type labels, not

...:$dst, (SPsjlj_setjmp ADDRri:$buf))]>, + Requires<[Is32Bit]>; + def EH_SJLJ_SETJMP32rr : Pseudo<(outs IntRegs:$dst), (ins MEMrr:$buf), + "#EH_SJLJ_SETJMP32", + [(set i32:$dst, (SPsjlj_setjmp ADDRrr:$buf))]>, + Requires<[Is32Bit]>; + let isTerminator = 1 in + def EH_SJLJ_LONGJMP32ri : Pseudo<(outs), (ins MEMri:$buf), + "#EH_SJLJ_LONGJMP32", + [(SPsjlj_longjmp ADDRri:$buf)]>, +...

I have updated TableGen to support a new format for instruction selection patterns. Before: def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>; After: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; Since the pattern matching happens on a DAG with type labels, not register classes, I think it makes more sense to specify types directly on the input

Hi, I'm trying to implement __builtin_setjmp / __builtin_longjmp for Sparc processors. I think I'm very close, but I can't work out how to issue BuildMI-type instructions to load the address of the recovery location (set in setjmp) into a register using the SETHI / OR combination. I can't see any equivalent code anywhere else in Sparc. I imagine this is similar if I try to make a

I have a rudimentary implementation for load and store instructions, where the memory address operand is automatically post-incremented when the load or store instruction is issued. However, this is currently coded using custom lowering, and explicit pattern matching in the 'ISelDAGtoDAG' implementation. But it seems to me that I ought to be able to achieve this exclusively using