search for: cpuregs

Displaying 20 results from an estimated 27 matches for "cpuregs".

2008 Apr 27
2
[LLVMdev] Questions for new Backend
Hi, I am trying to do a backend to a very simple microcontroller. I have some questions. 1) I have instruction which do "r1 <- r1 op r2", from what I have ssen I must declare them like: let isTwoAddress = 1 in def ADD : FopRR< 0b01010, (outs CPURegs:$sX), (ins CPURegs:$isX, CPURegs:$sY), "ADD $sX, $sY"), [(set CPURegs:$sX, (add CPURegs:$isX, CPURegs:$sY))]>; Where CPURegs is my class of register. I suppose that the pass TwoAddressInstructionPass will make the $sX and $isX register the same (i...
2011 May 02
2
[LLVMdev] LiveVariables not updated in MachineBasicBlock::SplitCriticalEdge?
...ne IR and LiveVariables::ValInfo dump before and after PHI nodes elimination. 1. Before PHI nodes elimination. -Machine IR: BB#14: derived from LLVM BB %for.cond151.preheader Predecessors according to CFG: BB#12 BB#13 %vreg29<def> = PHI %vreg25, <BB#12>, %vreg28, <BB#13>; CPURegs:%vreg29,%vreg25,%vreg28 %vreg30<def> = PHI %vreg26, <BB#12>, %vreg27, <BB#13>; CPURegs:%vreg30,%vreg26,%vreg27 BNE %vreg81<kill>, %ZERO, <BB#17>; CPURegs:%vreg81 J <BB#15> Successors according to CFG: BB#15 BB#17 BB#15: derived from LLVM BB %for....
2008 Apr 27
0
[LLVMdev] Questions for new Backend
...to a very simple microcontroller. I have > some > questions. Ok. > 1) I have instruction which do "r1 <- r1 op r2", from what I have > ssen I > must declare them like: > > let isTwoAddress = 1 in > def ADD : FopRR< 0b01010, > (outs CPURegs:$sX), (ins CPURegs:$isX, CPURegs:$sY), > "ADD $sX, $sY"), > [(set CPURegs:$sX, (add CPURegs:$isX, CPURegs: > $sY))]>; > > Where CPURegs is my class of register. I suppose that the pass > TwoAddressInstructionPass will make the $sX...
2011 Jan 24
1
[LLVMdev] Question about porting LLVM - code selection without assembler feature
Hello David, Thanks for your example. Is that means that DAG pattern is consist of LLVM IR instruction?? I met an example [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] of MipsInstrInfo.td, but I can't find correspond LLVM IR instruction of "set" in "LLVM Language Reference Manual". Is that correspond to $dst = op $b, $c?? Would you mind to tell me whether there is a reference of all possible element...
2012 Mar 07
2
[LLVMdev] Question about post RA scheduler
...ine code for function PointToHPoint: Frame Objects: fi#-1: size=48, align=8, fixed, at location [SP+8] fi#0: size=32, align=8, at location [SP] Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 BB#0: derived from LLVM BB %entry SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 The first two stores write the values in argument registers $6 and $7 to frame object -...
2011 Oct 07
2
[LLVMdev] MIPS 32bit code generation
...ka <ahatanak at gmail.com> wrote: > Do you want to replace > > lui $2, %hi(g1) > addiu $2, $2, %lo(g1) > > with this? > la $2, g1 > > If that is the case, you can add this pattern. > > def op_la : Operand<i32>; > > def LA : > FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), > "la $dst, $addr0", [(set CPURegs:$dst, > (add (MipsHi tglobaladdr:$addr0), (MipsLo > tglobaladdr:$addr1)))], IIAlu>; > > Note that you still need to find a way to print "g1" instead of &quot...
2011 Dec 12
0
[LLVMdev] Pattern-matching a MOV instruction
...moving values directly from one register to another, or moving an immediate straight to a register, and I cannot figure out how to do this in LLVM. I originally tried matching something like [(set RegisterClass:$dest, RegisterClass:$src)] in my TargetInstrInfo.td: def MOVrr : MyInstrClass<(outs CPURegs:$dest), (ins CPURegs:$src), "mov $dest,$src", [(set CPURegs:$dest, CPURegs:$src)]>; However this matches very random inputs - such as (set RegisterClass:$dest, (or RegisterClass:$src1, RegisterClass:$src2)), which is just strange - and is obviously not correct - for a start, it only...
2011 Oct 06
0
[LLVMdev] MIPS 32bit code generation
Do you want to replace lui $2, %hi(g1) addiu $2, $2, %lo(g1) with this? la $2, g1 If that is the case, you can add this pattern. def op_la : Operand<i32>; def LA : FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), "la $dst, $addr0", [(set CPURegs:$dst, (add (MipsHi tglobaladdr:$addr0), (MipsLo tglobaladdr:$addr1)))], IIAlu>; Note that you still need to find a way to print "g1" instead of "%hi(g1)". On We...
2012 Mar 07
0
[LLVMdev] Question about post RA scheduler
...nt: > Frame Objects: > fi#-1: size=48, align=8, fixed, at location [SP+8] > fi#0: size=32, align=8, at location [SP] > Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 > > BB#0: derived from LLVM BB %entry > SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 > SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 > %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 > %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 > > > The first two stores write the values in argument registe...
2012 Mar 07
2
[LLVMdev] Question about post RA scheduler
...>  fi#-1: size=48, align=8, fixed, at location [SP+8] >>  fi#0: size=32, align=8, at location [SP] >> Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 >> >> BB#0: derived from LLVM BB %entry >>       SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 >>       SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 >>       %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 >>       %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 >> >> >> The first two stores...
2012 Oct 23
2
[LLVMdev] Debugging/Fixing 'Interval not live at use' errors
...ice or help anyone can give. I'm unsure if it's actually relevant, but the particular MachineInstr that is involved when the assertion is thrown is always a LDrli (load from an address given by a register + 32-bit immediate, to a register), which is defined as: def LDrli : Pseudo<(outs CPURegs:$dst), (ins MEMrli:$addr), "ld $dst,$addr", [(set CPURegs:$dst, (load ADDRrli:$addr))]>; Where ADDRrli and MEMrli are: def ADDRrli : ComplexPattern<i32, 2, "SelectADDRrli", [frameindex], []>; // Register + long immediate. def M...
2011 Oct 07
0
[LLVMdev] MIPS 32bit code generation
...lt;ahatanak at gmail.com> wrote: > Do you want to replace > > lui $2, %hi(g1) > addiu $2, $2, %lo(g1) > > with this? > la $2, g1 > > If that is the case, you can add this pattern. > > def op_la : Operand<i32>; > > def LA : > FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), > "la $dst, $addr0", [(set CPURegs:$dst, > (add (MipsHi tglobaladdr:$addr0), (MipsLo > tglobaladdr:$addr1)))], IIAlu>; > > Note that you still need to find a way to print "g1" instead of &quo...
2011 Oct 05
4
[LLVMdev] MIPS 32bit code generation
Hi, In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Thanks, -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh
2012 Mar 13
0
[LLVMdev] Question about post RA scheduler
...align=8, fixed, at location [SP+8] >>> fi#0: size=32, align=8, at location [SP] >>> Function Live Ins: %A0 in %vreg0, %A2 in %vreg1, %A3 in %vreg2 >>> >>> BB#0: derived from LLVM BB %entry >>> SW %vreg2, <fi#-1>, 4; mem:ST4[FixedStack-1+4] CPURegs:%vreg2 >>> SW %vreg1, <fi#-1>, 0; mem:ST4[FixedStack-1](align=8) CPURegs:%vreg1 >>> %vreg3<def> = COPY %vreg0; CPURegs:%vreg3,%vreg0 >>> %vreg4<def> = LDC1 <fi#-1>, 0; mem:LD8[%x2] AFGR64:%vreg4 >>> >>> >&gt...
2011 Oct 07
1
[LLVMdev] MIPS 32bit code generation
...ace > > > > lui $2, %hi(g1) > > addiu $2, $2, %lo(g1) > > > > with this? > > la $2, g1 > > > > If that is the case, you can add this pattern. > > > > def op_la : Operand<i32>; > > > > def LA : > > FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), > > "la $dst, $addr0", [(set CPURegs:$dst, > > (add (MipsHi tglobaladdr:$addr0), (MipsLo > > tglobaladdr:$addr1)))], IIAlu>; > > > > Note that you still need to find a way to print "...
2011 Jan 24
0
[LLVMdev] Question about porting LLVM - code selection without assembler feature
Lu Mitnick <king19880326 at gmail.com> writes: > Hello all, > > I am adding a new target into LLVM. However there is a assembler for > that target and I just want LLVM to generate assembly. I read the > document "Writing an LLVM Backend". I am wondering to know whether I > can ignore the Inst field in the following example: I'm not an expert here so I'll
2011 Jan 22
3
[LLVMdev] Question about porting LLVM - code selection without assembler feature
Hello all, I am adding a new target into LLVM. However there is a assembler for that target and I just want LLVM to generate assembly. I read the document "Writing an LLVM Backend". I am wondering to know whether I can ignore the Inst field in the following example: class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<32>
2010 Jul 06
0
[LLVMdev] Question on the use of TableGen
...ot;MBlaze", [v8i16], 128, [PR0, PR1, PR2, PR3]>; // PR0 - PR3 are registers defined before I want to have a new integer register file for a different type, e.g. v8i16. But then I got errors when running tblgen. Here is the error I got when modifying the MBlaze backend: BSLLI: (set CPURegs:i32:$dst, (shl:i32 CPURegs:i32:$b, (imm:{i32:v8i16})<<P:Predicate_immZExt5>>:$c)) ../../../bin/tblgen: error: Included from .../llvm/lib/Target/MBlaze/MBlaze.td:25: .../llvm/lib/Target/MBlaze/MBlazeInstrInfo.td:347:5: error: In BSLLI: Could not infer all types in pattern! def BSLLI...
2012 Aug 18
1
[LLVMdev] MIPS Register Pressure Limit.
Hello, why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM. Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120818/a8e4f353/attachment.html>
2019 Mar 14
2
inline assembly matching error
I'm trying to add support for inline assembly and I keep getting this error: <jal> "<inline asm>:1:2: error: invalid instruction" which is due to the fact that MatchInstructionImpl() returns Match_MnemonicFail. This function is tablegen'ed in XXXGenAsmMatcher.inc and for some reason it can't find JAL even though I can clearly see it in both MatchTable0[] and