search for: strr

Hi Timo, I'm using Debian backports.org dovecot-imapd, 1:1.1.13-2~bpo50+1. I've got two different issues, a reoccurring, seemingly harmless one about "Corrupted index cache file" (boring.txt) and one that went bonkers over the least few days (bt.txt) causing much spamming of the logs. I've made bt.txt stop happening by just rm'ing dovecot.index* : find Maildir/

Hi, I've just upgraded our dovecot installation from 1.0.15 to 1.1.13. This went smoothly and just worked -- thank you very much for writing such a high performance and robust piece of software. However, we have a shared mailbox that people can subscribe to. After upgrading to 1.1.13 ... dovecot tries to create a dovecot-acl-list file in the top level of this ... but it creates it

Hi, I was trying to get hyperlinks using xtable, but couldn't get the hyperlinks to function properly. For example, if I use ## Try to link NY times website to every figure in column 4 mat <- matrix(1:43,6,5) mat[,5] <- "http://nytimes.com" for(i in 1:nrow(mat)){ strr <- paste('<a href="', mat[i,5],'">', mat[i,4], '</a>', sep='') mat[i,4] <- strr } mat2 <- mat[,1:4] caption = 'test' mx <- xtable(mat2,caption=caption) tt = print(mx, type="html",include.rownames=F) tt1 <-...

...let Pattern = pattern; } Second, I have read the documentation of "TableGen Fundamentals" and "The LLVM Target Independent Code Generator". But I don't know how to fill the dag filed of instruction. like [(store IntRegs:$src, ADDRrr:$addr)] of the following example: def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; Would anyone mind to tell me where to find the documentation of the dag in Independent Code Generator?? thanks a lot yi-hong --------------...

...> Second, I have read the documentation of "TableGen Fundamentals" and > "The LLVM Target Independent Code Generator". But I don't know how to > fill the dag filed of instruction. like [(store IntRegs:$src, > ADDRrr:$addr)] of the following example: > > def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), > > "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; > > Would anyone mind to tell me where to find the documentation of the > dag in Independent Code Generator?? Think of the DAG...

...the documentation of "TableGen Fundamentals" and > > "The LLVM Target Independent Code Generator". But I don't know how to > > fill the dag filed of instruction. like [(store IntRegs:$src, > > ADDRrr:$addr)] of the following example: > > > > def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), > > > > "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; > > > > Would anyone mind to tell me where to find the documentation of the > > dag in Independent Code Gene...

Hi all, I started to write an LLVM backend for custom CPU. I created XXXInstrInfo but there are some problems. I searched for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let