search for: f3_1

...define the lowering rules for this instruction, but I feel that this isn't likely to work as I need to somehow tie together the fact that %Y, %ASR18 and %rd are all related to each other in the output. let Predicates = [HasLeon3, HasLeon4], Defs = [Y, ASR18], Uses = [Y, ASR18] in def SMACrr : F3_1<3, 0b111110, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), "smac $rs1, $rs2, $rd", [(set i32:$rd, (add i32:$asr18, (mul i32:$rs1, i32:$rs2)))] >; Perhaps a well-chosen "let Constrain...

...tax for this, or do you need to be able to be able to automatically emit it from some higher level construct? I'd expect the former would be entirely sufficient, in which case this should be sufficient: let Predicates = [HasLeon3, HasLeon4], Defs = [Y, ASR18], Uses = [Y, ASR18] in def SMACrr : F3_1<3, 0b111110, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), "smac $rs1, $rs2, $rd", []>; If you want the latter, I'm not sure how you'd go about being able to pattern-match it, because of the unusual 40 bit accumulate...

Hi, I'm not sure. But in your lowered DAG the chain nodes are the first operands for you custom nodes, however for the other nodes the chain is the last operand. I seem to remember that during targetlowering the chain is the first operand and then it seems to switch over after ISelDAG, this confused me and may have something to do with the issue that you are seeing. I really don't

...d RegClass size = 4, align = 4 > > The GlobalAddress for variable c is replaced by an ADD(HI(c), LO > (c)) during lowering. I assume the code-generator cant place values > in the address registers? All address-registers are elements in the > register sets IntRegs and AddrRegs. /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { def rr : F3_1<2, Op3Val, (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), !strconcat(OpcStr, " $b, $c, $dst&quo...

...attern = pattern; } Second, I have read the documentation of "TableGen Fundamentals" and "The LLVM Target Independent Code Generator". But I don't know how to fill the dag filed of instruction. like [(store IntRegs:$src, ADDRrr:$addr)] of the following example: def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; Would anyone mind to tell me where to find the documentation of the dag in Independent Code Generator?? thanks a lot yi-hong -------------- next pa...

Hi! I'm writing a new back-end for a new architecture. First, I'll do some "tests" with an existing back-end (I chose the Sparc back-end). My architecture has special address-registers and I want to add such new address-registers to my Sparc back-end. 1) I defined a new register call AddrRegs 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) 3) I

...ond, I have read the documentation of "TableGen Fundamentals" and > "The LLVM Target Independent Code Generator". But I don't know how to > fill the dag filed of instruction. like [(store IntRegs:$src, > ADDRrr:$addr)] of the following example: > > def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), > > "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; > > Would anyone mind to tell me where to find the documentation of the > dag in Independent Code Generator?? Think of the DAG pattern...

...;> .... >> The GlobalAddress for variable c is replaced by an ADD(HI(c), LO >> (c)) during lowering. I assume the code-generator cant place values >> in the address registers? All address-registers are elements in the >> register sets IntRegs and AddrRegs. > > /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. > multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { > .... > } > > defm ADD : F3_12<"add", 0b000000, add>; > > Instruction ADD output register class is IntRegs. It does not...

...ch = EntryToken [ORD=1] [ID=0] 0x170db60: i16 = Register %reg16387 [ORD=1] [ID=1] 0x170ec00: i16 = Constant<0> [ORD=1] [ID=8] 0x170ef00: ch = BasicBlock<bb1 0x170a5d8> [ID=10] In my InstrInfo.td file I'm trying to match BRCOND as follows: let isBranch = 1 in def CondBranch : F3_1<2, 0b000101, (outs), (ins IntRegs:$L, i16imm:$R, brtarget:$dst), "; TODO: do conditional branching.", [(brcond (seteq IntRegs:$L, simm8:$R), bb:$dst)]>; I know CondBranch only handles SETEQ, but it should still match the code above (which...

Jakob Stoklund Olesen wrote: > I have updated TableGen to support a new format for instruction selection patterns. > > Before: > > def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>; > > After: > > def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; > > Since the pattern matching happens on a DAG with type labels, not

...gen: http://llvm.org/docs/TableGenFundamentals.html#multiclass Basically this lets you use one definition to implement multiple different instructions. For example, most instructions in the sparc target come in "reg,reg" and "reg,imm" forms. As such, it defines: multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { def rr : F3_1<2, Op3Val, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), !strconcat(OpcStr, " $b, $c, $dst"), [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;...

...mentation of "TableGen Fundamentals" and > > "The LLVM Target Independent Code Generator". But I don't know how to > > fill the dag filed of instruction. like [(store IntRegs:$src, > > ADDRrr:$addr)] of the following example: > > > > def STrr : F3_1< 3, 0b000100, (outs), (ins MEMrr:$addr, IntRegs:$src), > > > > "st $src, [$addr]", [(store IntRegs:$src, ADDRrr:$addr)]>; > > > > Would anyone mind to tell me where to find the documentation of the > > dag in Independent Code Generator??...

I have updated TableGen to support a new format for instruction selection patterns. Before: def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>; After: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; Since the pattern matching happens on a DAG with type labels, not register classes, I think it makes more sense to specify types directly on the input

Hi, I'm trying to implement a new backend for an embedded CISC processor. Therefore I thought that it makes sense to take X86 target as a basis, to save some time. But when I look into the X86InstrInfo.td, I have a very strong feeling that it is one of the most complex instruction set descriptions compared to other targets. I can imagine that this is due to the complexity of X86's

Hi all, I started to write an LLVM backend for custom CPU. I created XXXInstrInfo but there are some problems. I searched for it but I couldn't find anything. Can anyone help me? include "XXXInstrFormats.td" def simm16 : Operand<i32> { let DecoderMethod = "DecodeSimm16"; } def mem : Operand<i32> { let PrintMethod = "printMemOperand"; let

...ulticlass This is very interesting. > Basically this lets you use one definition to implement multiple different > instructions. For example, most instructions in the sparc target come in > "reg,reg" and "reg,imm" forms. As such, it defines: > > multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { > def rr : F3_1<2, Op3Val, > (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), > !strconcat(OpcStr, " $b, $c, $dst"), > [(set IntRegs:$dst, (OpNode IntRegs:$b, I...

...ption, I have the following patterns: //cmp (setcc) instruction def CMPri : F1<0b0000001101, (outs CondRegs:$cd), (ins GPRegs:$rn, uimm8:$uimm8), "c7 cmp\tne, $cd, $rn, $uimm8", [(set CondRegs:$cd, (setne GPRegs:$rn, uimmZExt8:$uimm8))]>; //conditional branch def BRcondrel : F3_1<0b011110, (outs), (ins CondRegs:$cd, brtarget:$offset), "$cd br\t$offset", [(brcond CondRegs:$cd, bb:$offset)]>; I want to place the setcc result in a condition reg and then do the conditional branch with the result from the condition reg. Unfortunately, thi...