llvm dev - Jul 2012 - [LLVMdev] Vector promotion broken for <2 x [i8|i16]>

No, that is correct. I am adding the new types so that I can bitcast v2i8 into a
v1i16 and then perform the 'and' operation and have legalize types turn
the v1i16 into a scalar.

Though I am having trouble in understanding how  x86 supports the <1 x
i64> type. Based on looking at the code, it should fail because v1i64 is not
supported on the x86 platform as far as I can tell.

Micah

From: Rotem, Nadav [mailto:nadav.rotem at intel.com]
Sent: Saturday, July 28, 2012 12:56 PM
To: Villmow, Micah; Developers Mailing List
Subject: RE: Vector promotion broken for <2 x [i8|i16]>

I think that you attached the wrong patch. The attached patch is the one which
adds the new MVT types.



From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Villmow, Micah
Sent: Saturday, July 28, 2012 01:54
To: Developers Mailing List
Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>

Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The
problem is in the VectorLegalizer::PromoteVectorOp.
The function getTypeToPromoteTo will return a <2 x i32> for a <2 x
i8>, <2 x i16> or <4 x i8>. The problem is that there are no
vectors of size 1 defined for i32 or i16. The attached patch fixes these issues.

This can be reproduced by setting in any target:
setOperationAction(ISD::AND, MVT::i8, Promote);
setOperationAction(ISD::AND, MVT::v2i8, Promote);
setOperationAction(ISD::AND, MVT::i16, Promote);

Let me know if this is good,
Micah

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>Though I am having trouble in understanding how  x86 supports the <1 x
i64> type. Based on looking at the code, it should fail because v1i64 is not
supported on the x86 platform as >far as I can tell.
The Type-Legalizer can handle vector types in the following ways:
1. Split - this splits vectors into two halves.  For example on SSE4, <4 x
i64>  is split to <2 x i64>
2. Widen - this methods adds additional vector elements, but keeps the element
type. For example <3 x float> is legalized to <4 x float>
3. Promote - this method widens each element in the vector. For example SSE
masks are promoted from <4 x i1> to <4 x i32>
4. Scalarize - this method coverts vectors with a single element into a scalar.
For example, <1 x i64> into i64.
>> The function getTypeToPromoteTo will return a <2 x i32> for a
<2 x i8>, <2 x i16> or <4 x i8>.
The first two conversions look correct, and I assume that your target declares
v2i32 as a legal type. I am not sure how <4 x i8> got there. Maybe it was
first split, and after that promoted ?



From: Rotem, Nadav [mailto:nadav.rotem at intel.com] 
Sent: Saturday, July 28, 2012 12:56 PM
To: Villmow, Micah; Developers Mailing List
Subject: RE: Vector promotion broken for <2 x [i8|i16]>

I think that you attached the wrong patch. The attached patch is the one which
adds the new MVT types.



From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Villmow, Micah
Sent: Saturday, July 28, 2012 01:54
To: Developers Mailing List
Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>

Vector promotion which is new in LLVM 3.1 is broken for sub32 bit types. The
problem is in the VectorLegalizer::PromoteVectorOp.
The function getTypeToPromoteTo will return a <2 x i32> for a <2 x
i8>, <2 x i16> or <4 x i8>. The problem is that there are no
vectors of size 1 defined for i32 or i16. The attached patch fixes these issues.

This can be reproduced by setting in any target:
setOperationAction(ISD::AND, MVT::i8, Promote);
setOperationAction(ISD::AND, MVT::v2i8, Promote);
setOperationAction(ISD::AND, MVT::i16, Promote);

Let me know if this is good,
Micah

---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
---------------------------------------------------------------------
Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

Sorry, <4 x i8> should convert to a <1 x i32>. What currently is
happening is that it is returning a <2 x i32> because <1 x i32> does
not exist.

Micah
> -----Original Message-----
> From: Rotem, Nadav [mailto:nadav.rotem at intel.com]
> Sent: Monday, July 30, 2012 10:51 AM
> To: Villmow, Micah; Developers Mailing List
> Subject: RE: Vector promotion broken for <2 x [i8|i16]>
> 
> 
> >Though I am having trouble in understanding how  x86 supports the <1
x
> i64> type. Based on looking at the code, it should fail because v1i64
> is not supported on the x86 platform as >far as I can tell.
> 
> The Type-Legalizer can handle vector types in the following ways:
> 1. Split - this splits vectors into two halves.  For example on SSE4,
> <4 x i64>  is split to <2 x i64>
> 2. Widen - this methods adds additional vector elements, but keeps the
> element type. For example <3 x float> is legalized to <4 x
float>
> 3. Promote - this method widens each element in the vector. For example
> SSE masks are promoted from <4 x i1> to <4 x i32>
> 4. Scalarize - this method coverts vectors with a single element into a
> scalar. For example, <1 x i64> into i64.
> 
> >> The function getTypeToPromoteTo will return a <2 x i32> for
a <2 x
> i8>, <2 x i16> or <4 x i8>.
> 
> The first two conversions look correct, and I assume that your target
> declares v2i32 as a legal type. I am not sure how <4 x i8> got there.
> Maybe it was first split, and after that promoted ?
> 
> 
> 
> From: Rotem, Nadav [mailto:nadav.rotem at intel.com]
> Sent: Saturday, July 28, 2012 12:56 PM
> To: Villmow, Micah; Developers Mailing List
> Subject: RE: Vector promotion broken for <2 x [i8|i16]>
> 
> I think that you attached the wrong patch. The attached patch is the
> one which adds the new MVT types.
> 
> 
> 
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
cs.uiuc.edu]
> On Behalf Of Villmow, Micah
> Sent: Saturday, July 28, 2012 01:54
> To: Developers Mailing List
> Subject: [LLVMdev] Vector promotion broken for <2 x [i8|i16]>
> 
> Vector promotion which is new in LLVM 3.1 is broken for sub32 bit
> types. The problem is in the VectorLegalizer::PromoteVectorOp.
> The function getTypeToPromoteTo will return a <2 x i32> for a <2 x
i8>,
> <2 x i16> or <4 x i8>. The problem is that there are no vectors
of size
> 1 defined for i32 or i16. The attached patch fixes these issues.
> 
> This can be reproduced by setting in any target:
> setOperationAction(ISD::AND, MVT::i8, Promote);
> setOperationAction(ISD::AND, MVT::v2i8, Promote);
> setOperationAction(ISD::AND, MVT::i16, Promote);
> 
> Let me know if this is good,
> Micah
> 
> ---------------------------------------------------------------------
> Intel Israel (74) Limited
> 
> This e-mail and any attachments may contain confidential material for
> the sole use of the intended recipient(s). Any review or distribution
> by others is strictly prohibited. If you are not the intended
> recipient, please contact the sender and delete all copies.
> ---------------------------------------------------------------------
> Intel Israel (74) Limited
> 
> This e-mail and any attachments may contain confidential material for
> the sole use of the intended recipient(s). Any review or distribution
> by others is strictly prohibited. If you are not the intended
> recipient, please contact the sender and delete all copies.