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...go about submitting a patch? Thanks, Javier [Original] /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift /// of any size. bool DAGTypeLegalizer:: ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue Amt = N->getOperand(1); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); EVT ShTy = Amt.getValueType(); unsigned NVTBits = NVT.getSizeInBits(); assert(isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"); DebugLoc dl = N->getDebugLoc(); /...

On Mon, Nov 30, 2009 at 7:22 PM, Javier Martinez <javier at jmartinez.org> wrote: > Hello, > > I'm working in adding support for 64-bit integers to my target. I'm using > LLVM to decompose the 64-bit integer operations by using 32-bit registers > wherever possible and emulating support where not. When looking at the bit > shift decomposition I saw what seems to be a

On Wed, 12 Aug 2020 at 13:11, Nicolas Kovacs <info at microlinux.fr> wrote: > Le 11/08/2020 ? 17:42, Kaushal Shriyan a ?crit : > > I am running CentOS Linux release 8.2.2004 (Core). Are there any > > instructions to install OpenVAS for CentOS Linux release 8.2.2004 (Core)? > > > > Thanks in advance and I look forward to hearing from you. > > For what

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...emove dead nodes now. + DAG.RemoveDeadNodes(); + + return Changed; +} + +SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) { + MVT VT = Op.getValueType(); + assert(Op.getNode()->getNumValues() == 1 && + "Can't promote a vector with multiple results!"); + MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); + DebugLoc dl = Op.getDebugLoc(); + SmallVector<SDValue, 4> Operands(Op.getNumOperands()); + + for (unsigned j = 0; j != Op.getNumOperands(); ++j) { + if (Op.getOperand(j).getValueType().isVector()) + Operands[j] = DAG.getNode(ISD::BIT_...

The LegalizeDAG.cpp file has this code in SelectionDAGLegalize::PromoteNode: case ISD::BSWAP: { unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); Results.push_back(Tmp1);...

...her values have similar > errors. Below is the current and proposed expansion in pseudo C++ for > all shift functions. Please let me know if I something is unclear. I'm not sure what you are saying, here is the code for shift-left. In the case of your example, Amt = 6, VTBits = 64 and NVTBits = 32. I've added comments at the end of various lines, like this: <== Comment. if (N->getOpcode() == ISD::SHL) { <== This branch is taken if (Amt > VTBits) { <== False ... not executed ... } else if (Amt > NVTBits) { <== False ... not executed ... }...

...sically just bitcasting and doing the operation // in a different type. For example, x86 promotes ISD::AND on v2i32 to // v1i64. EVT VT = Op.getValueType(); assert(Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"); EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); DebugLoc dl = Op.getDebugLoc(); SmallVector<SDValue, 4> Operands(Op.getNumOperands()); for (unsigned j = 0; j != Op.getNumOperands(); ++j) { if (Op.getOperand(j).getValueType().isVector()) Operands[j] = DAG.getNode(ISD::BITCAST, d...

On Dec 22, 2009, at 2:38 PMPST, Bill Wendling wrote: > The LegalizeDAG.cpp file has this code in > SelectionDAGLegalize::PromoteNode: > > case ISD::BSWAP: { > unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); > Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); > Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); > Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, > DAG.getConstant(DiffBits, > TLI.getShiftAmountTy())); >...

...the HowToUseJIT example by replacing the Int32Ty with another size (let's say 12 bits for the example). While it compiles ok, I get the following assert at run-time: HowToUseJIT: LegalizeDAG.cpp:4059: llvm::SDOperand <unnamed>::SelectionDAGLegalize::PromoteOp(llvm::SDOperand): Assertion `NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && "Cannot promote to smaller type!"' failed. The corresponding code is the following: SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { MVT::ValueType VT = Op.getValueType(); MVT::ValueType NVT = TLI.g...

...sically just bitcasting and doing the operation // in a different type. For example, x86 promotes ISD::AND on v2i32 to // v1i64. EVT VT = Op.getValueType(); assert(Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"); EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); DebugLoc dl = Op.getDebugLoc(); SmallVector<SDValue, 4> Operands(Op.getNumOperands()); for (unsigned j = 0; j != Op.getNumOperands(); ++j) { if (Op.getOperand(j).getValueType().isVector()) Operands[j] = DAG.getNode(ISD::BITCAST, d...

Hi Duncan, The problem is the implementation of the expansion. Perhaps an example can help illustrate better. Take the case of a 64-bit integer shifted left by say 6 bits and is decomposed using 32-bit registers. Because 6 is less than the 32 (the register size) the resulting low part should be equal to the source low part shifted left by 6 bits. The current implementation places a zero

...t; operation > // in a different type. For example, x86 promotes ISD::AND on v2i32 > to > // v1i64. > EVT VT = Op.getValueType(); > assert(Op.getNode()->getNumValues() == 1 && > "Can't promote a vector with multiple results!"); > EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); > DebugLoc dl = Op.getDebugLoc(); > SmallVector<SDValue, 4> Operands(Op.getNumOperands()); > > for (unsigned j = 0; j != Op.getNumOperands(); ++j) { > if (Op.getOperand(j).getValueType().isVector()) > Operands[j]...

...; operation > // in a different type. For example, x86 promotes ISD::AND on v2i32 > to > // v1i64. > EVT VT = Op.getValueType(); > assert(Op.getNode()->getNumValues() == 1 && > "Can't promote a vector with multiple results!"); > EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); > DebugLoc dl = Op.getDebugLoc(); > SmallVector<SDValue, 4> Operands(Op.getNumOperands()); > > for (unsigned j = 0; j != Op.getNumOperands(); ++j) { > if (Op.getOperand(j).getValueType().isVector()) > Operands[j]...

...umber of elements that is not a power of two are always - // widened, for example <3 x float> -> <4 x float>. + // widened, for example <3 x i8> -> <4 x i8>. if (!VT.isPow2VectorType()) { NumElts = (unsigned)NextPowerOf2(NumElts); EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); + while (!isTypeLegal(NVT)) { + NumElts = (unsigned)NextPowerOf2(NumElts); + NVT = EVT::getVectorVT(Context, EltVT, NumElts); + } return LegalizeKind(TypeWidenVector, NVT); } From: llvmdev-bounces at cs.u...

...ry indicating that FP_TO_UINT should be expanded for these value types, but the actual expansion is in target-independent code. This is what it looks like in the version I last fetched: case ISD::FP_TO_UINT: { SDValue True, False; EVT VT = Node->getOperand(0).getValueType(); EVT NVT = Node->getValueType(0); APFloat apf(DAG.EVTToAPFloatSemantics(VT), APInt::getNullValue(VT.getSizeInBits())); APInt x = APInt::getSignBit(NVT.getSizeInBits()); (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); Tmp1 = DAG.getConstantFP(apf, dl, VT...

...andShiftWithKnownAmountBit(N, Lo, Hi)) { <== The call returns False ... } if (N->getOpcode() == ISD::SHL) { <== Branch taken PartsOpc = ISD::SHL_PARTS; } else if (N->getOpcode() == ISD::SRL) { ... } else { ... } if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || Action == TargetLowering::Custom) { <== False ... } if (N->getOpcode() == ISD::SHL) { <== Branch taken } else if (N->getOpcode() == ISD::SRL) { ... } else { ... } if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { <== Returns False as I set the l...

I don't know how your target architecture looks like, but I suspect that <4 x i8> should not be legalized to <1 x i32>. I think that what you are seeing is that <4 x i8> is first split into <2 x i8>, and later promoted to <2 x i32>. At the moment different targets can only affect type-legalization by declaring different legal types. A number of us discussed the

...Sanjay, > > > > The issue that Michael is talking about is that in SelectionDAGLegalize::ExpandNode() > we’re doing this: > > > > case ISD::FP_TO_UINT: { > > SDValue True, False; > > EVT VT = Node->getOperand(0).getValueType(); > > EVT NVT = Node->getValueType(0); > > APFloat apf(DAG.EVTToAPFloatSemantics(VT), > > APInt::getNullValue(VT.getSizeInBits())); > > APInt x = APInt::getSignMask(NVT.getSizeInBits()); > > (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);...