Pranav Bhandarkar
2012-Jul-05 05:45 UTC
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
Hi, This question relates to the undef flag in the context of sub-register def operands. 1) Firstly, the documentation (comments in the source code) says that in a sub-register def operand, the "IsUndef" flag refers to the part of the register that is not written. 2) Further, the documentation about readsReg() states that a sub-register def implicitly reads the other parts of the register being redefined unless the <undef> flag is set. Now, I am writing a pass the splits the following sequence of MIs MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. MI2:: B<def> = C & A ; C and B are also 64bit super regs. Into NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg. NewMI_2:: B:hi_sub_reg<def> = 0 The question is how should I be setting up the <undef> flags on the def operands of NewMI_1 and 2 ? Should I set the <undef> flag only on NewMI_1 because in NewMI_2 lo_sub_reg has already been defined by NewMI_1? Or should the <undef> flags be set in both as per 2 above ? TIA, Pranav Qualcomm Innovation Center, (QuIC) is a member of the Code Aurora Forum.
Jakob Stoklund Olesen
2012-Jul-05 15:44 UTC
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
On Jul 4, 2012, at 10:45 PM, Pranav Bhandarkar <pranavb at codeaurora.org> wrote:> Hi, > > This question relates to the undef flag in the context of sub-register def > operands. > > 1) Firstly, the documentation (comments in the source code) says that in a > sub-register def operand, the "IsUndef" flag refers to the part of the > register that is not written. > 2) Further, the documentation about readsReg() states that a sub-register > def implicitly reads the other parts of the register being redefined unless > the <undef> flag is set. > > Now, I am writing a pass the splits the following sequence of MIs > > MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. > MI2:: B<def> = C & A ; C and B are also 64bit super regs. > > Into > NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg. > NewMI_2:: B:hi_sub_reg<def> = 0 > > The question is how should I be setting up the <undef> flags on the def > operands of NewMI_1 and 2 ? Should I set the <undef> flag only on NewMI_1 > because in NewMI_2 lo_sub_reg has already been defined by NewMI_1? > Or should the <undef> flags be set in both as per 2 above ?The <undef> flag goes on NewMI_1 because the virtual register B isn't live before that instruction. But you probably shouldn't be doing this yourself. Your NewMI code isn't in SSA form because B has multiple definitions. Just use a REG_SEQUENCE instruction, and let the register allocator do the transformation for you. /jakob
Pranav Bhandarkar
2012-Jul-05 15:53 UTC
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
Hi Jakob, Thanks for your reply.> > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn'tin> SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation for you.Aaargh. So you mean something like this ? New_MI_1:: Vreg1 = 0 ; Vreg1 and Vreg2 are 32 bit virt. regs. New_MI_2:: Vreg2 = COPY C:lo_sub_reg. New_MI_3:: B= REG_SEQUENCE<Vreg1, hi_sub_reg, Vreg2, lo_sub_reg> ; B is a 64 bit virt reg. TIA, Pranav
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- [LLVMdev] MachineOperand: Subreg defines and the Undef flag
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- [LLVMdev] MachineOperand: Subreg defines and the Undef flag