search for: newmi

...\ .addReg(X86::new_reg, kill).addImm(i) for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE; ++MFI) { MachineBasicBlock* MBB = MFI; for (MachineBasicBlock::iterator MBBI = MBB->begin(); MBBI != MBB->end(); ++MBBI) { MachineInstr *NewMI = NULL; OldMI = MBBI; // %EFLAGS<imp-def> is getting copied // %RDX<imp-use,kill> is not getting copied (when it appears) switch (OldMI->getOpcode()) { default: continue; // .... case X86::BT64ri8: case X86::BT32ri8:...

...having difficulty with the basic block surgery of replacing the old MachineInst. The peephole pass gets called per MachineFunction and then iterates over each MachineBasicBlock and in turn over each MachineInst. When it finds an instruction which should be replaced, it builds a new instruction: NewMI = BuildMI(*MBB, MBBI, MBBI->getDebugLoc(), TII->get(X86::opcode)) .addReg(X86::new_reg, kill) .addImm(i); This works and it correctly places the new instruction just before the old instruction in the assembly output. So far so good. Now I have to remove the old instruction. But ever...

...= [2808,2810:0)[2810,2811:1) 0 at 2808 1 at 2810 Mapped %reg2559 and folded instruction: %reg2559<def> = ADD64rr %reg2559, %reg1579, %EFLAGS<imp-def,dead> ; srcLine 0 into: ADD64mr <fi#165>, 1, %reg0, 0, %reg1579, %mreg23<imp-def,dead> ; srcLine 0 Virt folded mapped NewMI 0x9405f70: ADD64mr <fi#165>, 1, %reg0, 0, %reg1579, %mreg23<imp-def,dead> ; srcLine 0 to %reg2559 +[2820,2822:0) Added new interval: %reg2565,0 = [2820,2822:0) 0 at 2820 Mapped %reg2559 and folded instruction: %reg2559<def> = ADD64rr %reg2559, %reg1599<kill>, %EFLAG...

...unless > the <undef> flag is set. > > Now, I am writing a pass the splits the following sequence of MIs > > MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. > MI2:: B<def> = C & A ; C and B are also 64bit super regs. > > Into > NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg. > NewMI_2:: B:hi_sub_reg<def> = 0 > > The question is how should I be setting up the <undef> flags on the def > operands of NewMI_1 and 2 ? Should I set the <undef> flag only on NewMI_1 > because in NewMI_2 lo_sub_...

...BuildMI(*MBB, OldMI, MBBI->getDebugLoc(), TII->get(X86::opcode)) \ .addReg(X86::new_reg, kill).addImm(i) I didn't completely understand your other proposed change: ​ for (MachineBasicBlock::iterator MBBI = MBB->begin(); MBBI != MBB->end(); ) { MachineInstr *NewMI = NULL; OldMI = MBBI; ++MBBI; I think you're saying with ++MBBI to step past the old instruction. This seems faster speedwise but more of a hack than just restarting the loop. But I'll try it. It implies a certain knowledge of the iterator and MBB. I accidentally touched Machi...

...other parts of the register being redefined unless the <undef> flag is set. Now, I am writing a pass the splits the following sequence of MIs MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. MI2:: B<def> = C & A ; C and B are also 64bit super regs. Into NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg. NewMI_2:: B:hi_sub_reg<def> = 0 The question is how should I be setting up the <undef> flags on the def operands of NewMI_1 and 2 ? Should I set the <undef> flag only on NewMI_1 because in NewMI_2 lo_sub_reg has already been defi...

...MachineVerifier because the newly created tBL insn by Thumb1InstrInfo::foldMemoryOperandImpl had memory operands of LoadMI attached by TargetInstrInfo::foldMemoryOperand, which is done unconditionally: // Copy the memoperands from the load to the folded instruction. if (MI.memoperands_empty()) { NewMI->setMemRefs(MF, LoadMI.memoperands()) In this case, we don't want the memory loads to be added to MI from LoadMI. Should there be some mechanism for target specific foldMemoryOperandImpl hook to signal to foldMemoryOperand to not add memory operands from LoadMI ? I was wondering if either...

...--------- Index: lib/CodeGen/TailDuplication.cpp =================================================================== --- lib/CodeGen/TailDuplication.cpp (revision 211103) +++ lib/CodeGen/TailDuplication.cpp (working copy) @@ -453,6 +453,11 @@ } } PredBB->insert(PredBB->instr_end(), NewMI); + + /// If there is bundled instruction in TailBB, + /// make bundled instruction in PredBB. + if (MI->isBundled() && MI->isInsideBundle()) + NewMI->bundleWithPred(); } /// UpdateSuccessorsPHIs - After FromBB is tail duplicated into its predecessor

Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do...

...created tBL insn by > Thumb1InstrInfo::foldMemoryOperandImpl had memory operands of LoadMI > attached by TargetInstrInfo::foldMemoryOperand, which is done > unconditionally: > > // Copy the memoperands from the load to the folded instruction. > if (MI.memoperands_empty()) { > NewMI->setMemRefs(MF, LoadMI.memoperands()) > > In this case, we don't want the memory loads to be added to MI from > LoadMI. Should there be some mechanism for target specific > foldMemoryOperandImpl hook to signal to foldMemoryOperand to not add > memory operands from LoadMI ? &gt...

...); + if (CI != Candidates.end()) { + MachineOperand &MO = I->getOperand(0); + MachineInstr *CMI = CI->second; + + if (MO.getReg() == CMI->getOperand(2).getReg()) { + DEBUG(dbgs() << "Commuting: " << *I); + MachineInstr *NewMI = TII->commuteInstruction(I,false); + assert(NewMI && "failed to commute the operands!"); + + DEBUG(dbgs() << "NewMI is: " << *NewMI); + DEBUG(dbgs() << "Removing redundant insert: " << *CMI); + CMI...

There are 11 BuildMI() functions in MachineInstrBuilder.h including four using the iterator and one using an instruction. But I just don't think that's it. The creation of the new instruction works fine (works fine with OldMI as well) and the new instruction is present in the assembly output. The problem is removing the old instruction correctly. > The loop header needs to be

...MachineOperand &JumpTarget = MBBI->getOperand(0); + + assert (MBBI->getOpcode() == ARM::TCRETURNri); + DebugLoc dl = MBBI->getDebugLoc(); + + BuildMI(MBB, MBBI, dl, + TII.get(ARM::tTAILJMPr)) + .addReg(JumpTarget.getReg(), RegState::Kill); + + MachineInstr *NewMI = std::prev(MBBI); + for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) + NewMI->addOperand(MBBI->getOperand(i)); + + // Delete the pseudo instruction TCRETURN. + MBB.erase(MBBI); + MBBI = NewMI; + return; + } + // Unlike T2 and ARM mode, the T1 pop instr...

...// allocated. If not, bail out now. >> + const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII; >> + int NewOpcode = GetDotNewOp(MI->getOpcode()); >> + const MCInstrDesc&desc = QII->get(NewOpcode); >> + DebugLoc dl; >> + MachineInstr *NewMI = MI->getParent()->getParent()->CreateMachineInstr(desc, dl); >> + bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI); >> + MI->getParent()->getParent()->DeleteMachineInstr(NewMI); >> + >> + if (!ResourcesAvailable) >> +...