search for: machineoperand

Jakob and anyone else who might be interested... Base on this patch back in August, I sense some need to double check with you whether it is OK to start making a heavy use of MachineOperand TargetFlags? We do seem to have a compelling reason for it in Hexagon, and I wanted to make sure that it is OK with everyone. I plan to use it for attributing target specific info to MOs and in more general case to MIs that those MOs belongs to. Part of my question would be - is it still unsafe t...

I have a MachineOperand that could be something other than a Reg: mem, global address, imm, etc... I want to replace a reg MachineOperand with this non-reg MachineOperand. I've tried a few different things, but it doesn't seem like there is some simple functionality to do this? "RemoveOperand" and &qu...

...in CodeGen that deals with register operands does not appropriately handle target flags on the register operand (it might not transfer the information from an "old" operand to an "updated" operand). I guess I am asking you to clarify what you mean by heavy use of TargetFlags on MachineOperands. What specifically do you plan to do? Jakob, TargetFlags on immediate machine operands introduced as early as ISel Lowering should not be a problem, right? Thanks, Arnold On Mon, Oct 29, 2012 at 12:17 PM, Sergei Larin <slarin at codeaurora.org> wrote: > > Jakob and anyone else who...

Is there any way to determine if a Register-type MachineOperand represents a fixed machine register? For example, call arguments must end up in specific machine register but I don't see any way to ascertain this from the information in MachineOperand. Basically, I need to know if I am allowed to rename a MachineOperand or not after register allocation. T...

How do I determine what type of register(i.e. i32, f32, etc..) I am accessing from a MachineOperand? I.e. how do I get to the MVT struct, or equivalent information, from a MachineOperand object? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. 4555 Great America Pkwy, Santa Clara, CA. 95054 P: 408-572-6219 F: 408-572-6596 ------------...

I'm looking at utilizing the MachineOperand::TargetFlags and I'm wondering if there is a specific reason on limiting the size of the flags to 8 bits. Also are there any assumptions on what can be validly used here that I should keep in mind? Ideally I need 28 bits but I can code the major cases using all 8 bits, but I don't want to c...

...ssage----- > From: Arnold Schwaighofer [mailto:arnolds at codeaurora.org] > Sent: Monday, October 29, 2012 1:02 PM > To: Sergei Larin > Cc: Jakob Stoklund Olesen; llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] [llvm-commits] [llvm] r162770 - in /llvm/trunk: > include/llvm/CodeGen/MachineOperand.h lib/CodeGen/MachineInstr.cpp > > Hi Sergei, > > our use of target flags will be on immediate register operands if I am > not mistaken (and if not we can always encode it as such)? > > I guess you are refering to the hexagon backend needing to distinguish > between insta...

You can get to the MachineInstr from a MachineOperand. Then get to its TargetInstrDesc and TargetOperandInfo which has register class information. Evan On Sep 23, 2008, at 12:44 PM, Villmow, Micah wrote: > How do I determine what type of register(i.e. i32, f32, etc..) I am > accessing from a MachineOperand? I.e. how do I get to the MVT...

...r registers. Thanks, ________________________________ From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Wednesday, September 24, 2008 10:22 AM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Determining the register type of a MachineOperand You can get to the MachineInstr from a MachineOperand. Then get to its TargetInstrDesc and TargetOperandInfo which has register class information. Evan On Sep 23, 2008, at 12:44 PM, Villmow, Micah wrote: How do I determine what type of register(i.e. i32, f32, etc..) I am accessing...

On Oct 18, 2010, at 11:59 AM, Villmow, Micah wrote: > I’m looking at utilizing the MachineOperand::TargetFlags and I’m wondering if there is a specific reason on limiting the size of the flags to 8 bits. We create *LOTS* of MachineOperand instances, so it needs to be as small as possible. > Also are there any assumptions on what can be validly used here that I should keep in mind? Ideally...

On May 16, 2013, at 2:23 PM, dag at cray.com wrote: > Is there any way to determine if a Register-type MachineOperand > represents a fixed machine register? For example, call arguments must > end up in specific machine register but I don't see any way to ascertain > this from the information in MachineOperand. Basically, I need to know > if I am allowed to rename a MachineOperand or not after reg...

...ould have the operators match in the tblgen. We are looking to avoid this, we thought a simple peephole would do the trick instead. On Tue, Jun 16, 2015 at 9:57 AM, Tom Stellard <tom at stellard.net> wrote: > On Mon, Jun 15, 2015 at 10:16:47PM -0400, Ryan Taylor wrote: > > I have a MachineOperand that could be something other than a Reg: mem, > > global address, imm, etc... > > > > I want to replace a reg MachineOperand with this non-reg MachineOperand. > > > > I've tried a few different things, but it doesn't seem like there is some > > simple fu...

To my knowledge, I don't think there is an easy way to get the MVT information from a MachineOperand. Why do you need it for? In my mind, the MachineInstr and its associated operands represent a physical machine instruction and I typically want to think of those as machine opcodes and machine register files. I am typically interested in the mapping of MVTs to register classes when I...

On Aug 6, 2012, at 11:00 AM, Vincent Lejeune <vljn at ovi.com> wrote: > Ok. > > I tried to do it using a pass after register allocation, lowering NEG/ABS instructions. > However I met a problem : apparently getNextOperandForReg() can returns a MachineOperand before the one I'm processing. > > The following code snippet : > > > void R600ModifiersPropagation::substituteReg(MachineOperand &def_MO, unsigned new_reg, unsigned char flag) { > MachineOperand * MO = def_MO.getNextOperandForReg(); > while (MO && MO-&g...

All, The code generator operand class, MachineOperand, has an 8-bit TargetFlags field that the individual targets can use as they please. X86 and ARM use it to encode linker magic on symbol operands. It has been mentioned a couple of times on this list that it is not safe to use TargetFlags on register operands. This is because many target-independen...

...statistics on machine code using LLVMs MachineInstr, etc., infrastructure. My current goal is to count the number of bytes of integer and floating point data being processed per iteration of a loop. Now I've ran into the problem that I can't find any obvious way to get the actual type of a MachineOperand. After some digging I noticed that the selection DAG has some type information and I had a look at the TableGen records that contain this type info. I started looking into how I could generate some descriptor tables with that information but TableGen is quite a handfull, and I'd like to avoid...

...on, but is not optimal as it costs an extra (often uneeded) MOV instruction. I'm trying to rework this : I'd like that a "DST = FNEG SRC" custom Emitter lowering pass replaces every occurence of DST by SRC and set the corresponding TargetFlag in the process. Something like this : MachineOperand *MO = &(MI->getOperand(0)); while(MO) {   MachineOperand *next_MO = MO->getNextOperandForReg();   MO->addTargetFlag(MO_FLAG_NEG);   MO->setReg(MI->getOperand(1).getReg());   MO = next_MO; } As far as I can tell, this works as every register are still virtual when lowering custo...

Hi all, I have a question about the types of MachineOperand. There are 12 different types of MachineOperand such as MO_Register, MO_Immediate and so on. Some of the names are self-explanatory such as MO_Register and MO_Immediate. Some of them are a little confusing such as MO_FrameIndex, MO_ConstantPoolIndex and so on. For example, what is the different...

On Mon, Aug 20, 2012 at 04:30:13PM -0700, Jakob Stoklund Olesen wrote: > All, > > The code generator operand class, MachineOperand, has an 8-bit TargetFlags field that the individual targets can use as they please. X86 and ARM use it to encode linker magic on symbol operands. > > It has been mentioned a couple of times on this list that it is not safe to use TargetFlags on register operands. This is because many target-...

I'm working on the post-regalloc dataflow engine I mentioned yesterday. Currently I only need to track register operands. A MachineOperand has both a getReg() and a getSubReg() interface. For a physical register operand, is getReg() guaranteed to be the "most super" register with getSubReg() providing the specific subregister information for the operand? If so then for my current purposes it seems I don't need to worry...