search for: mi1

Dear R-Users, I used the box.tidwell () function of the car Package. When I used the following formula: semi.sub.in.mi1.boxtidwell_h<-box.tidwell(RENT_LG ~ I(age+1)+I(age2+1)+X06A + I(X08B+1) + I(X22+1) + I(X24+1) + X31A, ~B_YEAR + C_X01 + C_X14 + C_X19 + C_X29A +C_X21 + C_X23 + D_X12 + D_X17 + D_X18 + D_X25 + D_X27 + D_X30 + D_X32 + D_X35, data = semi.sub.in.mi1) everything is fine. However, when I repla...

Hi all, I am working on an out-of-tree target. I am wondering if it is possible to force the register allocator (and/or spiller) to not break certain instruction sequence. For example: phys_reg = MI1 vreg1 vreg 2 = MI2 phys_reg Is there a way to tell RA/spiller not to insert COPY or spill between MI1 and MI2? I am using greedy register allocator and inline spiller. -- Regards, Dongrui -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/p...

...LUE instructions for spills does not seem to be handling insert locations inside bundles well. If the spill instruction is part of a bundle, the new DBG_VALUE is inserted after it, but does not have the bundling flags set. This essentially means that if we start with a set of bundled instructions: MI1 [BundledSucc=true, BundledPred=false] MI2 [BundledSucc=false, BundledPred=true] Where MI1 is a spill, and MI2 is a different instruction, after ExtendRanges we end up with MI1 [BundledSucc=true, BundledPred=false] DBG_VALUE MI [BundledSucc=false, BundledPred=false] MI2 [BundledSucc=false, Bund...

...LUE instructions for spills does not seem to be handling insert locations inside bundles well. If the spill instruction is part of a bundle, the new DBG_VALUE is inserted after it, but does not have the bundling flags set. This essentially means that if we start with a set of bundled instructions: MI1 [BundledSucc=true, BundledPred=false] MI2 [BundledSucc=false, BundledPred=true] Where MI1 is a spill, and MI2 is a different instruction, after ExtendRanges we end up with MI1 [BundledSucc=true, BundledPred=false] DBG_VALUE MI [BundledSucc=false, BundledPred=false] MI2 [BundledSucc=false, Bund...

...t1, $S), (G_TRUNC $D, $t1), (isScalarType type:$D), (isLargerType type:$D, type:$S)), (apply (G_ZEXT $D, $S))>; def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1), (match (G_ZEXT $t0, $S):$MI0, (G_TRUNC $D, $t0):$MI1), (isScalarType type:$D), (isLargerType type:$D, type:$S)), (apply (G_ZEXT $D, $S, (debug_locations $MI...

...> def : GICombineRule<(defs reg:$D, reg:$S), >> (match (G_ZEXT $t1, $S), >> (G_TRUNC $D, $t1), >> (isScalarType type:$D), >> (isLargerType type:$D, type:$S)), >> (apply (G_ZEXT $D, $S))>; >> def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1), >> (match (G_ZEXT $t0, $S):$MI0, >> (G_TRUNC $D, $t0):$MI1), >> (isScalarType type:$D), >> (isLargerType type:$D, type:$S)), >> (apply (G_ZEXT $D, $S, (debug_locations $MI0, $MI1)))>; >> def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1...

...have this situation. A3 = B0 ..... ..... B1 = A3 <--The copy C And if so, we check if we can merge the two ranges of B into a single range. However, this is not safe if A3 is a subreg define while A3 is not a subreg use. For instance, consider this code (part of a single block loop). MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, 2, // Post Inc. Load. Vreg7 is a 64bit reg. MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> // This is the A3 = B0 above. MI3:: %vreg31<def> = ADD_rr %vreg31<kill>, %vreg32...

Hi Jakob, Thanks for your reply. > > The <undef> flag goes on NewMI_1 because the virtual register B isn't live > before that instruction. > > But you probably shouldn't be doing this yourself. Your NewMI code isn't in > SSA form because B has multiple definitions. Just use a REG_SEQUENCE > instruction, and let the register allocator do the transformation

........ > B1 = A3 <--The copy C > > And if so, we check if we can merge the two ranges of B into a single range. > However, this is not safe if A3 is a subreg define while A3 is not a subreg > use. > For instance, consider this code (part of a single block loop). > > MI1:: %vreg7:subreg_loreg<def,undef>, %vreg30<def> = POST_LDriuh %vreg30, > 2, // Post Inc. Load. Vreg7 is a 64bit reg. > MI2:: %vreg7:subreg_hireg<def> = COPY %vreg32:subreg_hireg<kill> > // This is the A3 = B0 above. > MI3:: %vreg31<def> = ADD_rr %vreg31&...

...s to the part of the register that is not written. 2) Further, the documentation about readsReg() states that a sub-register def implicitly reads the other parts of the register being redefined unless the <undef> flag is set. Now, I am writing a pass the splits the following sequence of MIs MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. MI2:: B<def> = C & A ; C and B are also 64bit super regs. Into NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg. NewMI_2:: B:hi_sub_reg<def> = 0 The question is how should I be setting up the <undef&g...

...ate to better match the order in the underlying function prototype. Preserving DILocation and other debug info We have a choice of syntax here and neither seems to be clearly better than the other when considering just locations: def : GICombineRule<(defs reg:$D, reg:$S, instr:$MI0, instr:$MI1), (match (G_ZEXT $t0, $S):$MI0, (G_TRUNC $D, $t0):$MI1), (isScalarType type:$D), (isLargerType type:$D, type:$S)), (apply (G_ZEXT $D, $S, (debug_locations $MI...

...;LM1" ,"LM2" ,"LM3", "DB1" ,"DB2" ,"DB3", "DM1" , "DM2" , "DM3" , "FI1", "FI2", "BKI1", "BKI2", "BKO1", "BKO2", "BKO3", "SUR1","MI1","MI2","MI3","BHE1","BHE2","BHE3","BHW1","BHW2","BHW3","HAL1","HAL2","HAL3","HAL4","HAL5","HAL6","HAL7","DOH1","DOH2","...

> On Nov 10, 2018, at 03:28, Nicolai Hähnle <nhaehnle at gmail.com> wrote: > > Thank you for the detailed reply! There's a lot to digest :) Let me try to address most of it. > > > [snip] >>> I also think you should have 'ins' and 'outs' separately; after all, a predicate may have to do a combined check on two matched registers / operands,

...is not written. > 2) Further, the documentation about readsReg() states that a sub-register > def implicitly reads the other parts of the register being redefined unless > the <undef> flag is set. > > Now, I am writing a pass the splits the following sequence of MIs > > MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. > MI2:: B<def> = C & A ; C and B are also 64bit super regs. > > Into > NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg. > NewMI_2:: B:hi_sub_reg<def> = 0 > > The question is how sho...

...penswan-2.6.32/programs/pluto/ikev1_main.c:1112: st->st_sec_in_use==FALSE Mar 7 16:24:53 firewall pluto[7647]: "ciscovpntest" #2: using kernel interface: netkey .... Mar 7 16:24:53 firewall pluto[7647]: "ciscovpntest" #2: #2: "ciscovpntest":500 STATE_MAIN_I1 (sent MI1, expecting MR1); EVENT_RETRANSMIT in 39s; nodpd; idle; import:admin initiate Mar 7 16:24:53 firewall pluto[7647]: "ciscovpntest" #2: #2: pending Phase 2 for "ciscovpntest" replacing #0 Downgrading openswan to openswan-2.6.32-27.el6.i686 solves the problem. The problem is restr...

...essentially expresses the following correspondence: opcode ==> {FU1, FU2, ...} and DFAPacketizer uses DFA with opcodes. In order to strictly schedule predicated instructions like SVE, We need to consider that following two instructions use pipeline resources exclusively in the same cycle: MI1 if P ==> {FU1, FU2, ...} MI2 if Q ==> {FU1, FU2, ...} where predicate P and Q hold P == not Q. However, I don't think that current DFAPacketizer can represent these situations. References: [1] Code Generation Schemas for Modulo Scheduled DO-loops and WHILE-loops http://www.hpl.hp.com...

...oteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI, >> + unsigned DepReg, >> + std::map<MachineInstr*, SUnit*> MIToSUnit); >> + bool DemoteToDotOld(MachineInstr* MI); >> + bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2, >> + std::map<MachineInstr*, SUnit*> MIToSUnit); >> + bool RestrictingDepExistInPacket(MachineInstr*, >> + unsigned, std::map<MachineInstr*, SUnit*>); >> + bool isNewifiable(MachineInstr* MI); >&...