Displaying 3 results from an estimated 3 matches for "newmi_1".
2012 Jul 05
2
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
...other parts of the register being redefined unless
the <undef> flag is set.
Now, I am writing a pass the splits the following sequence of MIs
MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg.
MI2:: B<def> = C & A ; C and B are also 64bit super regs.
Into
NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg.
NewMI_2:: B:hi_sub_reg<def> = 0
The question is how should I be setting up the <undef> flags on the def
operands of NewMI_1 and 2 ? Should I set the <undef> flag only on NewMI_1
because in NewMI_2 lo_sub_reg has already been define...
2012 Jul 05
0
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
...unless
> the <undef> flag is set.
>
> Now, I am writing a pass the splits the following sequence of MIs
>
> MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg.
> MI2:: B<def> = C & A ; C and B are also 64bit super regs.
>
> Into
> NewMI_1:: B:lo_sub_reg<def> = COPY C:lo_sub_reg.
> NewMI_2:: B:hi_sub_reg<def> = 0
>
> The question is how should I be setting up the <undef> flags on the def
> operands of NewMI_1 and 2 ? Should I set the <undef> flag only on NewMI_1
> because in NewMI_2 lo_sub_re...
2012 Jul 05
3
[LLVMdev] MachineOperand: Subreg defines and the Undef flag
Hi Jakob,
Thanks for your reply.
>
> The <undef> flag goes on NewMI_1 because the virtual register B isn't live
> before that instruction.
>
> But you probably shouldn't be doing this yourself. Your NewMI code isn't
in
> SSA form because B has multiple definitions. Just use a REG_SEQUENCE
> instruction, and let the register allocator do th...