search for: readsreg

...rewrite: 5056r Reg5:lo16<def> = mv_nimm6_ar16 0 So it inserts a reload of the full Reg5 prior to the setting of Reg5:lo16, because it thinks there is an implicit use of Reg5 when writing the low part??? This seems very weird to me. The decision is based on the fact that MachineOperand::readsReg() returns true: /// readsReg - Returns true if this operand reads the previous value of its /// register. A use operand with the <undef> flag set doesn't read its /// register. A sub-register def implicitly reads the other parts of the /// register being redefined unle...

...node isn't one we're interested in, advance to one that // we are interested in. if (op) { if ((!ReturnUses && op->isUse()) || - (!ReturnDefs && op->isDef()) || + (!ReturnDefs && op->isDef() && !op->readsReg()) || (SkipDebug && op->isDebug())) advance(); } } friend class MachineRegisterInfo; @@ -907,11 +907,11 @@ public: else assert(!Op->isDebug() && "Can't have debug defs"); }...

...g the partial update clearance / dependency breaking mechanism for some ARM cores. It seems that the ARM specific code for this will always return a clearance of 0 for VLD1LNd32 because of the following code in getPartialRegUpdateClearance: > if (UseOp != -1 && MI->getOperand(UseOp).readsReg()) > return 0; so essentially VLD1LNd32 (and potentially other instruction) will never be affected by this. Was this intended or is there a bug here? I'm confused why the dependency breaking code is correct. Why would the dependency breaking mechanism apply only when the register is de...

...eg19:lo16<def,read-undef> = COPY %vreg73 is redefining the whole vreg19, not only the lo16 part, and since this instruction has read-undef, it thinks no part of vreg19, not even hi16 is live over instruction 880. >> >> isUndef() will return false and getSubReg() true, and thus readsReg() >> true and the reload is inserted. >> >> Then we get >> >> *** Bad machine code: Instruction loads from dead spill slot *** >> >> because the spill slot has not been written. > > This is weird. Any chance you could share a test case? Unfortunately...

...ependency breaking mechanism > for some ARM cores. > > It seems that the ARM specific code for this will always > return a clearance of 0 for VLD1LNd32 because of the following > code in getPartialRegUpdateClearance: > >> if (UseOp != -1 && MI->getOperand(UseOp).readsReg()) >> return 0; > > so essentially VLD1LNd32 (and potentially other instruction) > will never be affected by this. Was this intended or is there > a bug here? > > I'm confused why the dependency breaking code is correct. > Why would the dependency breaking mechan...

...ion relates to the undef flag in the context of sub-register def operands. 1) Firstly, the documentation (comments in the source code) says that in a sub-register def operand, the "IsUndef" flag refers to the part of the register that is not written. 2) Further, the documentation about readsReg() states that a sub-register def implicitly reads the other parts of the register being redefined unless the <undef> flag is set. Now, I am writing a pass the splits the following sequence of MIs MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. MI2:: B<def> = C & A...

...ter updates versus full register updates. >> <snip> > > MachineOperand handles this. You just need to create the machine instrs. > > Interesting. I couldn't find how to do it. It would be great if somebody helps me on this. I was thinking of APIs like MachineOperand::readsReg(). I guess if you’re only asking whether an instruction zeros the upper part of the register, that information *should* be available from MCInstr/MCRegisterInfo, but I’m not very familiar with the API. Matthias? -Andy > 1) Partial register updates versus full register updates. > > On...

...aterializablePossible(*DefMI, aa)) return false; DEBUG(dbgs() << " ComplexRemat MI: " << *DefMI); for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = DefMI->getOperand(i); if (!MO.isReg() || !MO.getReg() || !MO.readsReg()) continue; if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { if (MRI.isConstantPhysReg(MO.getReg(), *DefMI->getParent()->getParent())) continue; //If not constant then check its def if(depth > 6) return false; LiveInterval &...

...in the context of sub-register def > operands. > > 1) Firstly, the documentation (comments in the source code) says that in a > sub-register def operand, the "IsUndef" flag refers to the part of the > register that is not written. > 2) Further, the documentation about readsReg() states that a sub-register > def implicitly reads the other parts of the register being redefined unless > the <undef> flag is set. > > Now, I am writing a pass the splits the following sequence of MIs > > MI1:: A<def> = 0xFFFFFFFF ; A is a 64bit super reg. >...

Hi Andrew, Thanks for the feedback! On Fri, Mar 2, 2018 at 1:16 AM, Andrew Trick <atrick at apple.com> wrote: > > On Mar 1, 2018, at 9:22 AM, Andrea Di Biagio <andrea.dibiagio at gmail.com> > wrote: > > Hi all, > > At Sony we developed an LLVM based performance analysis tool named > llvm-mca. We > currently use it internally to statically measure the