llvm dev - Jul 2019 - Question about TableGen RegisterClass definition

Hi All,

I have a question about TableGen RegisterClass definition.

I need to map different size of MVTs into a register class as below.

def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>

When I look at TableGen and CodeGen, it looks the types are used as following:

1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction pattern matching
>From my opinion, it seems it is possible to do it... but I am not 100%
sure... If anyone has information about it, please give me comment.
Thanks


JinGu Kang
Software Engineer
Codeplay Software Ltd
Level C Argyle House, 3 Lady Lawson Street, Edinburgh, United Kingdom, EH3
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Ping!

I would like to check whether we can map multiple MVTs with different size to
one register class as below.

def TestReg : RegisterClass<"Test", [v32i16, v32i32], ...>

The register classes could be used as below.

def : Pat<(v32i16 (add TestRegs:$src0, TestRegs:$src1)),
           (vaddv32i16 $src0, $src1)>;

def : Pat<(v32i32 (add TestRegs:$src0, TestRegs:$src1)),
           (vaddv32i32 $src0, $src1)>;

Is it possible to implement above register class and pattern? I could create
different register class per each MVT with different size... but it is not
preferred internally... If anyone has information about above one, please share
it.

Thanks

JinGu Kang

________________________________
From: JinGu Kang
Sent: 18 July 2019 15:03
To: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org>
Subject: Question about TableGen RegisterClass definition

Hi All,

I have a question about TableGen RegisterClass definition.

I need to map different size of MVTs into a register class as below.

def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>

When I look at TableGen and CodeGen, it looks the types are used as following:

1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction pattern matching
>From my opinion, it seems it is possible to do it... but I am not 100%
sure... If anyone has information about it, please give me comment.
Thanks


JinGu Kang
Software Engineer
Codeplay Software Ltd
Level C Argyle House, 3 Lady Lawson Street, Edinburgh, United Kingdom, EH3
9DR<http://maps.google.co.uk/?q=EH3%209DR>
Tel: +44 (0)131 466 0503
Website: http://www.codeplay.com<http://www.codeplay.com/>
Twitter: https://twitter.com/codeplaysoft

This email and any attachments may contain confidential and /or privileged
information and is for use by the addressee only. If you are not the intended
recipient, please notify Codeplay Software Ltd immediately and delete the
message from your computer. You may not copy or forward it, or use or disclose
its contents to any other person. Any views or other information in this message
which do not relate to our business are not authorized by Codeplay software Ltd,
nor does this message form part of any contract unless so stated.
As internet communications are capable of data corruption Codeplay Software Ltd
does not accept any responsibility for any changes made to this message after it
was sent. Please note that Codeplay Software Ltd does not accept any liability
or responsibility for viruses and it is your responsibility to scan any
attachments.
Company registered in England and Wales, number: 04567874
Registered office: Regent House, 316 Beulah Hill, London, United Kingdom, SE19
3HF

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Sorry... I made a mistake from below definition.

def TestReg : RegisterClass<"Test", [v32i16, v32i32], ...>
--->
def TestReg : RegisterClass<"Test", [v32i32, v32i16], ...>

TableGen takes the size of register class from first type on the type list. In
this case, the bigger size is correct.

Thanks
JinGu Kang

________________________________
From: JinGu Kang <jingu at codeplay.com>
Sent: 22 July 2019 09:55
To: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org>
Subject: Re: Question about TableGen RegisterClass definition

Ping!

I would like to check whether we can map multiple MVTs with different size to
one register class as below.

def TestReg : RegisterClass<"Test", [v32i16, v32i32], ...>

The register classes could be used as below.

def : Pat<(v32i16 (add TestRegs:$src0, TestRegs:$src1)),
           (vaddv32i16 $src0, $src1)>;

def : Pat<(v32i32 (add TestRegs:$src0, TestRegs:$src1)),
           (vaddv32i32 $src0, $src1)>;

Is it possible to implement above register class and pattern? I could create
different register class per each MVT with different size... but it is not
preferred internally... If anyone has information about above one, please share
it.

Thanks

JinGu Kang

________________________________
From: JinGu Kang
Sent: 18 July 2019 15:03
To: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org>
Subject: Question about TableGen RegisterClass definition

Hi All,

I have a question about TableGen RegisterClass definition.

I need to map different size of MVTs into a register class as below.

def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>

When I look at TableGen and CodeGen, it looks the types are used as following:

1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction pattern matching
>From my opinion, it seems it is possible to do it... but I am not 100%
sure... If anyone has information about it, please give me comment.
Thanks


JinGu Kang
Software Engineer
Codeplay Software Ltd
Level C Argyle House, 3 Lady Lawson Street, Edinburgh, United Kingdom, EH3
9DR<http://maps.google.co.uk/?q=EH3%209DR>
Tel: +44 (0)131 466 0503
Website: http://www.codeplay.com<http://www.codeplay.com/>
Twitter: https://twitter.com/codeplaysoft

This email and any attachments may contain confidential and /or privileged
information and is for use by the addressee only. If you are not the intended
recipient, please notify Codeplay Software Ltd immediately and delete the
message from your computer. You may not copy or forward it, or use or disclose
its contents to any other person. Any views or other information in this message
which do not relate to our business are not authorized by Codeplay software Ltd,
nor does this message form part of any contract unless so stated.
As internet communications are capable of data corruption Codeplay Software Ltd
does not accept any responsibility for any changes made to this message after it
was sent. Please note that Codeplay Software Ltd does not accept any liability
or responsibility for viruses and it is your responsibility to scan any
attachments.
Company registered in England and Wales, number: 04567874
Registered office: Regent House, 316 Beulah Hill, London, United Kingdom, SE19
3HF

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