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Please open a bugzilla ticket and attach your testcase. It will allow us to debug and fix the problem. Thanks - Elena From: JinGu [mailto:jingu at codeplay.com] Sent: Saturday, September 16, 2017 00:38 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com> Cc: llvm-dev at lists.llvm.org Subje...

...()); > } else { > return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr, MachinePointerInfo(), EltVT); > } I assume that we need the opposite - if (.. < 8) getExtLoad // VT should be MVT::i8, MemVT should be MVT::i1 else getLoad - Elena From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Monday, September 18, 2017 13:40 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at gmail.com> Cc: llvm-dev at lists....

Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the M...

> extends the elements to 8bit and stores them on stack. Store is responsible for zero-extend. This is the policy... - Elena -----Original Message----- From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Friday, September 15, 2017 17:45 To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com Subject: Re: Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT' Can...

Hi Matthias, >Jingu: Why do you even want a configuration that has LLVM_ENABLE_DUMP but does not have asserts enabled at the same time? My colleague and I am doing custom project using clang/llvm. We have always wanted to use the IR Value's dump() to check our implementation correctly with Debug, Release and a...

...se if it /// was already in the set. std::pair<iterator, bool> insert(PtrType Ptr) { auto p = insert_imp(PtrTraits::getAsVoidPointer(Ptr)); return std::make_pair(iterator(p.first, CurArray + CurArraySize), p.second); } If the comment is changed, please change it. Thanks, JinGu Kang

On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote: > Hi Andy, > > I am trying to schedule and packetize instructions for VLIW at post-RA > stage or final codegen stage, where code transformations are not allowed > any more, because hardware can not resolve resource conflict. There is a > simp...

...dAdvance' only uses the 'WriteResourceID' field of 'MCWriteLatencyEntry' in 'computeOperandLatency' function. I think the pair of latency and write resource for defintion will be useful to check conflicts of resources. As reference, I have attached simple patch. Thanks, JinGu Kang -------------- next part -------------- Index: utils/TableGen/SubtargetEmitter.cpp =================================================================== --- utils/TableGen/SubtargetEmitter.cpp (revision 201607) +++ utils/TableGen/SubtargetEmitter.cpp (working copy) @@ -932,12 +932,7 @@ W...

...ut this? I did not find the API in order to make the first instruction of the bundle. I have added simple code to make bundled instructions from the 'DuplicateInstruction' function. As a reference, I have attached a simple patch. If there is something wrong, please let me know. Thanks, JinGu Kang -------------- next part -------------- Index: lib/CodeGen/TailDuplication.cpp =================================================================== --- lib/CodeGen/TailDuplication.cpp (revision 211103) +++ lib/CodeGen/TailDuplication.cpp (working copy) @@ -453,6 +453,11 @@ } } Pre...

...ter.cpp, once there is decoding conflict, tablegen does not generate table entry. I think it means even though there are predicates, it does not affect to the table entry. Could someone let me know how to avoid decoding conflict in this situation? If I missed something, please let me know. Thanks, JinGu Kang

...M, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: > Hi Andrew, > > We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models. > > To expand on what JinGu mentioned, our target has explicit ports that are used to read and write values from and to the register file. The read port is usually accessed on cycle 0 while the write port is accessed when the result is written back to the destination register. Let's assume ADD has a latency of 1, MUL has...

...cted with chain. I guess it assumes each vector element's address is different. The each store is lowered to load and store nodes with high and low address but they are not connected with the other store's one. It causes problem. I am not sure how to solve this situation correctly. Thanks, JinGu Kang 2016-01-29 18:11 GMT+00:00 Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org>: > On 1/29/2016 10:47 AM, JinGu Kang via llvm-dev wrote: >> >> >> I am doing it with lowering store as follow: >> >> 1. make low and high address with alignment. &g...

Hi Bruce, Thanks for response. I also think it is not good way. Do you have the other ways to legalize it? Thanks, JinGu Kang 2016-02-01 13:11 GMT+00:00 Bruce Hoult <bruce at hoult.org>: > In fact this is a pretty bad legalizing/lowering because you only need to > load and edit for the first and last values in the vector. The other words > are completely replaced and don't need to be loaded at all...

...lay.com> wrote: >> >>> Hi Andrew, >>> >>> We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models. >>> >>> To expand on what JinGu mentioned, our target has explicit ports that are used to read and write values from and to the register file. The read port is usually accessed on cycle 0 while the write port is accessed when the result is written back to the destination register. Let's assume ADD has a latency of 1, MUL has...

...v [mailto:llvm-dev-bounces at lists.llvm.org <mailto:llvm-dev-bounces at lists.llvm.org>] On Behalf Of Mehdi >> Amini via llvm-dev >> Sent: Sunday, April 09, 2017 2:26 PM >> To: Matthias Braun >> Cc: llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>; jingu at codeplay.com <mailto:jingu at codeplay.com> >> Subject: Re: [llvm-dev] Question about LLVM Building Error with "- >> DLLVM_ENABLE_DUMP" and "RelWithDebInfo" >> >> >>> On Apr 7, 2017, at 4:45 PM, Matthias Braun via llvm-dev <llvm- &g...

On Tue, Jun 28, 2016 at 2:45 AM, jingu kang via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Hi All, > > Can someone comment below question whether it is wrong or not please? > > 2016-06-25 7:52 GMT+01:00 jingu kang <jaykang10 at gmail.com>: >> Hi All, >> >> I have a problem with VectorLega...

...sts.llvm.org <mailto:llvm-dev-bounces at lists.llvm.org>] On Behalf Of Mehdi >>>> Amini via llvm-dev >>>> Sent: Sunday, April 09, 2017 2:26 PM >>>> To: Matthias Braun >>>> Cc: llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>; jingu at codeplay.com <mailto:jingu at codeplay.com> >>>> Subject: Re: [llvm-dev] Question about LLVM Building Error with "- >>>> DLLVM_ENABLE_DUMP" and "RelWithDebInfo" >>>> >>>> >>>>> On Apr 7, 2017, at 4:45 PM,...

...9;isUnsignedDIType' function and it generates assertion for 'DW_ATE_lo_user'. Is it intended? I think it should not generate assertion for 'DW_ATE_lo_user' because it comes from complex integer type. How do you think about it? If I missed something, please let me know. Thanks, JinGu Kang

...re and load carry bit with scratch register or make a pass to force to reload register spilled at a specific place. But I would like to check whether there are existing ways or better ways to solve this problem. Could someone let me know about it? If I missed something, please let me know. Thanks, JinGu Kang

...e used as following: 1. MCRegisterClass's RegSize and Alignment 2. SpillSize in TableGen 3. Type constraint for instruction pattern matching >From my opinion, it seems it is possible to do it... but I am not 100% sure... If anyone has information about it, please give me comment. Thanks JinGu Kang Software Engineer Codeplay Software Ltd Level C Argyle House, 3 Lady Lawson Street, Edinburgh, United Kingdom, EH3 9DR<http://maps.google.co.uk/?q=EH3%209DR> Tel: +44 (0)131 466 0503 Website: http://www.codeplay.com<http://www.codeplay.com/> Twitter: https://twitter.com/codeplaysof...