Displaying 12 results from an estimated 12 matches for "v32i32".
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v2i32
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
hello,
i need to use v32i32 and v32f32 in store instructions.
I defined my register as;
def VRR128 : RegisterClass<"X86", [v32i32, v32f32],
1024, (add R_0_V_0, R_1_V_0, R_2_V_0)>;
def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst,
VRR128:$src),...
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
...here to place v32f32 to distinguish between the two?
On Tue, Jul 11, 2017 at 7:55 PM, Craig Topper <craig.topper at gmail.com>
wrote:
> You need a type inside this bitconvert. The outer type is the destination
> type for the bitconvert but it also needs an input type
>
> (store (v32i32 (bitconvert VRR128:$src)), addr:$dst)
>
> On Tue, Jul 11, 2017 at 7:27 AM hameeza ahmed <hahmed2305 at gmail.com>
> wrote:
>
>> hello,
>> i need to use v32i32 and v32f32 in store instructions.
>> I defined my register as;
>>
>> def VRR128 : RegisterCl...
2017 Sep 21
1
VSelect Instruction Error
Hello,
I am getting this error. What instruction is required to be implemented?
LLVM ERROR: Cannot select: t22: v32i32 = vselect t724, t11, t16
t724: v32i32,ch = load<LD128[FixedStack1]> t723, FrameIndex:i64<1>,
undef:i64
t659: i64 = FrameIndex<1>
t10: i64 = undef
t11: v32i32,ch = load<LD128[%sunkaddr45](align=4)(tbaa=<0x481f1e8>)> t0,
t8, undef:i64
t8: i64 = add t7, Co...
2017 Jul 11
2
error: In anonymous_4820: Unrecognized node 'VRR128'!
...> On Tue, Jul 11, 2017 at 7:55 PM, Craig Topper <craig.topper at gmail.com>
>> wrote:
>>
>>> You need a type inside this bitconvert. The outer type is the
>>> destination type for the bitconvert but it also needs an input type
>>>
>>> (store (v32i32 (bitconvert VRR128:$src)), addr:$dst)
>>>
>>> On Tue, Jul 11, 2017 at 7:27 AM hameeza ahmed <hahmed2305 at gmail.com>
>>> wrote:
>>>
>>>> hello,
>>>> i need to use v32i32 and v32f32 in store instructions.
>>>> I defined m...
2019 Jul 18
2
Question about TableGen RegisterClass definition
Hi All,
I have a question about TableGen RegisterClass definition.
I need to map different size of MVTs into a register class as below.
def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>
When I look at TableGen and CodeGen, it looks the types are used as following:
1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
Hello,
i want to work with these types v32f32, v32f64.... in llvm which are
undefined in the backend?
But v32i32, v32i64 are already defined so i am able to use these.
but for other types such as v32f32, v32f64 although i have defined them
appropriately in all the files like machinevaluetype.h, valuetypes.cpp
etc. i have checked it many times but still getting the following error
when build in debug mode....
2018 Jul 24
2
KNL Vectorization with larger vector width
...so here when i keep iteration=2047 i get all
scalar why is that so? similarly in polly as well i cant see vector mixes
like its happening for KNL it emits <v16i32>, <v8i32>,<v4i32>...so here it
should emit recursively like <v2048i32> <v1024i32> <v512i32>.....<v32i32>
how to do this?
What am i missing here?
what further changes do i need to make?
Please help...
On Tue, Jul 24, 2018 at 1:52 AM, Friedman, Eli <efriedma at codeaurora.org>
wrote:
> On 7/23/2018 12:40 PM, hameeza ahmed wrote:
>
>> Thank You. I got it. Version issue.
&g...
2017 Jul 11
2
Using new types v32f32, v32f64 in llvm backend not possible
...ank You
On Tue, Jul 11, 2017 at 6:20 PM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> On 07/11/2017 03:22 AM, hameeza ahmed wrote:
>
>> Hello,
>>
>> i want to work with these types v32f32, v32f64.... in llvm which are
>> undefined in the backend?
>> But v32i32, v32i64 are already defined so i am able to use these.
>>
>> but for other types such as v32f32, v32f64 although i have defined them
>> appropriately in all the files like machinevaluetype.h, valuetypes.cpp
>> etc. i have checked it many times but still getting the followin...
2017 Jul 12
2
Using new types v32f32, v32f64 in llvm backend not possible
....gov> wrote:
>>
>>>
>>> On 07/11/2017 03:22 AM, hameeza ahmed wrote:
>>>
>>>> Hello,
>>>>
>>>> i want to work with these types v32f32, v32f64.... in llvm which are
>>>> undefined in the backend?
>>>> But v32i32, v32i64 are already defined so i am able to use these.
>>>>
>>>> but for other types such as v32f32, v32f64 although i have defined them
>>>> appropriately in all the files like machinevaluetype.h, valuetypes.cpp
>>>> etc. i have checked it many time...
2018 Jul 24
2
KNL Vectorization with larger vector width
...ion=2047 i get all
>> scalar why is that so? similarly in polly as well i cant see vector mixes
>> like its happening for KNL it emits <v16i32>, <v8i32>,<v4i32>...so here it
>> should emit recursively like <v2048i32> <v1024i32> <v512i32>.....<v32i32>
>>
>> how to do this?
>>
>> What am i missing here?
>> what further changes do i need to make?
>>
>> Please help...
>>
>>
>>
>>
>>
>>
>> On Tue, Jul 24, 2018 at 1:52 AM, Friedman, Eli <efriedma at codeaurora....
2020 Jun 30
5
[RFC] Semi-Automatic clang-format of files with low frequency
I 100% get that we might not like the decisions clang-format is making, but
how does one overcome this when adding new code? The pre-merge checks
enforce clang-formatting before commit and that's a common review comment
anyway for those who didn't join the pre-merge checking group. I'm just
wondering are we not all following the same guidelines?
Concerns of clang-format not being good
2018 Jul 23
2
KNL Vectorization with larger vector width
Thank You. I got it. Version issue.
TTI.getRegisterBitWidth(true)
How to put my target machine info in TTI?
Please help.
On Mon, Jul 23, 2018 at 11:33 PM, Friedman, Eli <efriedma at codeaurora.org>
wrote:
> On 7/23/2018 10:49 AM, hameeza ahmed via llvm-dev wrote:
>
> Thank You.
>
> But I cannot find your mentioned function