similar to: Question about TableGen RegisterClass definition

Displaying 20 results from an estimated 900 matches similar to: "Question about TableGen RegisterClass definition"

2018 Jun 11
4
One more No-alias case on Alias analysis
Hello All, I have met one may-alias case from llvm's alias analysis. The code snippet is as following: char buf[4]; void test (int idx) { char *a = &buf[3 - idx]; char *b = &buf[idx]; *a = 1; *b = 2; } I can see below output from alias set tracker for above code snippet. Alias sets for function 'test': Alias Set Tracker: 1 alias sets for 2 pointer values.  
2018 Jun 12
2
One more No-alias case on Alias analysis
On 06/11/2018 02:33 PM, Friedman, Eli via llvm-dev wrote: > On 6/11/2018 10:06 AM, jingu at codeplay.com via llvm-dev wrote: >> Hello All, >> >> I have met one may-alias case from llvm's alias analysis. The code >> snippet is as following: >> >> char buf[4]; >> >> void test (int idx) { >> char *a = &buf[3 - idx]; >> char *b =
2018 Jun 18
2
Question about Alias Analysis with restrict keyword
Hello All, I have met a case with restrict keyword and I have a question about it. Let's look at a simple example. char buf[4]; void test(char *restrict a, char *restrict b, int count) {   for (unsigned i = 0; i < count; i++) {     *a = *b;     a++;     b++;     buf[i] = i;   } } I think there are no aliasing among pointers such as 'a', 'b' and 'buf'
2017 Sep 17
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
Please open a bugzilla ticket and attach your testcase. It will allow us to debug and fix the problem. Thanks - Elena From: JinGu [mailto:jingu at codeplay.com] Sent: Saturday, September 16, 2017 00:38 To: Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com <daniel_l_sanders at apple.com>; Jon Chesterfield <jonathanchesterfield at
2017 Sep 15
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
> extends the elements to 8bit and stores them on stack. Store is responsible for zero-extend. This is the policy... - Elena -----Original Message----- From: jingu at codeplay.com [mailto:jingu at codeplay.com] Sent: Friday, September 15, 2017 17:45 To: llvm-dev at lists.llvm.org; Demikhovsky, Elena <elena.demikhovsky at intel.com>; daniel_l_sanders at apple.com Subject: Re: Question
2017 Sep 18
1
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
> so I think we need to use non-extending load for element size less than 8bit on "DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT" like this roughly. > if (N->getOperand(0).getValueType().getVectorElementType().getSizeInBits() < 8) { > return DAG.getLoad(N->getValueType(0), dl, Store, StackPtr, MachinePointerInfo()); > } else { > return
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
On Feb 19, 2014, at 1:54 PM, jingu <jingu at codeplay.com> wrote: > Hi Andy, > > I am trying to schedule and packetize instructions for VLIW at post-RA > stage or final codegen stage, where code transformations are not allowed > any more, because hardware can not resolve resource conflict. There is a > simple example as following: > > ADD dest_reg1, src_reg1,
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
On Mar 4, 2014, at 10:05 AM, Pete Cooper <peter_cooper at apple.com> wrote: > > On Mar 3, 2014, at 2:21 PM, Andrew Trick <atrick at apple.com> wrote: > >> >> On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: >> >>> Hi Andrew, >>> >>> We are currently using a custom model where
2017 Apr 10
2
Question about LLVM Building Error with "-DLLVM_ENABLE_DUMP" and "RelWithDebInfo"
Hi Matthias, >Jingu: Why do you even want a configuration that has LLVM_ENABLE_DUMP but does not have asserts enabled at the same time? My colleague and I am doing custom project using clang/llvm. We have always wanted to use the IR Value's dump() to check our implementation correctly with Debug, Release and another builds. We thought the LLVM_ENABLE_DUMP is for it. If Chris fixes
2017 Apr 10
5
Question about LLVM Building Error with "-DLLVM_ENABLE_DUMP" and "RelWithDebInfo"
Presently several of our headers have definitions like: #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) void dump() const; #endif Would it make sense to modify the build system to define LLVM_ENABLE_DUMP in config.h on debug builds? Then we could wrap dump methods just based on LLVM_ENABLE_DUMP instead of two variables. -Chris > On Apr 10, 2017, at 1:34 PM, Robinson, Paul via llvm-dev
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
On Mar 3, 2014, at 8:53 AM, Pierre-Andre Saulais <pierre-andre at codeplay.com> wrote: > Hi Andrew, > > We are currently using a custom model where scheduling information is attached to each MCInstrDesc through tablegen, and we're trying to move to one of LLVM's models. > > To expand on what JinGu mentioned, our target has explicit ports that are used to read and
2014 Dec 18
2
[LLVMdev] Please change the comment of 'insert' member function of SmallPtrSetImpl
Hi all, I have a compilation failure with 'insert' member function of SmallPtrSetImpl class because the return value is changed from r222334. But the comment of the function is same with before as follows: /// insert - This returns true if the pointer was new to the set, false if it /// was already in the set. std::pair<iterator, bool> insert(PtrType Ptr) { auto p
2017 Apr 09
3
Question about LLVM Building Error with "-DLLVM_ENABLE_DUMP" and "RelWithDebInfo"
> On Apr 7, 2017, at 4:45 PM, Matthias Braun via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > I think the idea is to keep NDEBUG out of headers when possible. So I think this should better be something like: > > -#ifndef NDEBUG > void dumpUses(unsigned RegNo) const; > -#endif > > to be inline with various other dumpers (like MachineInstr::dump(),
2017 Apr 10
2
Question about LLVM Building Error with "-DLLVM_ENABLE_DUMP" and "RelWithDebInfo"
> On Apr 10, 2017, at 12:37 PM, Matthias Braun <mbraun at apple.com> wrote: > > The situation is not consistent. Yes there are several places where we have the #if in the headers however there are far more cases where it is not. Some points here: > > - This whole LLVM_DUMP_FUNCTION/LLVM_ENABLE_DUMP is about enabling the linker to strip (or not strip) the dumping function in
2017 Sep 14
2
Question about 'DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT'
Hi All, I have a question about splitting 'EXTRACT_VECTOR_ELT' with 'v2i1'. I have a llvm IR code snippet as following: llvm IR code snippet: for.body: ; preds = %entry, %for.cond %i.022 = phi i32 [ 0, %entry ], [ %inc, %for.cond ] %0 = icmp ne <2 x i32> %vecinit1, <i32 0, i32 -23> %1 = extractelement <2 x i1>
2014 Feb 19
2
[LLVMdev] Question about per-operand machine model
Hi JinGu, We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved. Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.
2017 Apr 06
4
Question about LLVM Building Error with "-DLLVM_ENABLE_DUMP" and "RelWithDebInfo"
Hi All, I have tried to build llvm tip as following: cmake -DCMAKE_CXX_FLAGS:STRING="-DLLVM_ENABLE_DUMP" -DCMAKE_BUILD_TYPE=RelWithDebInfo ../llvm After running 'make', I have got error messages like below. llvm/lib/CodeGen/MachineRegisterInfo.cpp:462:67: error: no ‘void llvm::MachineRegisterInfo::dumpUses(unsigned int) const’ member function declared in class
2014 Dec 08
2
[LLVMdev] Question about '-fno-exceptions' option and 'ExceptionsType' on MCAsmInfo with ARM.
Hi all I have a question about the '-fno-exceptions' option with clang and 'ExceptionsType' on MCAsmInfo. I am looking for a way to avoid generating stack unwinding codes when compiling with the "armv7-none-linux-gnu" triple using clang. I tried the '-fno-exceptions' option in order to do that, but unwinding function symbols like
2014 Jun 17
2
[LLVMdev] Question about 'DuplicateInstruction' function of TailDuplicatePass in CodeGen
Hi all, I have faced a little bit of a strange transformation from the TailDuplicatePass In CodeGen. When the pass clones the contents of TailBB into PredBB, the bundled instructions in TailBB are not bundled in PredBB. I think the reason why it is not bundled is that the 'DuplicateInstruction' function does not set up the flag of the first instruction of the bundle in PredBB when it
2018 Jun 13
2
Question about a May-alias case
Hello All, I have a question about a May-alias case. Let's look at one simple C example. char *buf[4]; char c; void test(int idx) {   char *a = buf[3 - idx];   char *b = buf[idx];   *a = *b;   c++;   *a = *b; } We can imagine the second "*a = *b" could be removed. Let's look at the IR snippet with -O3 for above example.   1 define void @test(i32 %idx) {   2 entry: