search for: registerclass

I'm looking at an issue where we want a particular pseudo-instruction to choose from a set of registers that is not included in the existing set of RegisterClass definitions. More concretely, there is a RegisterClass in ARMRegisterInfo.td defined as def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)]; let AltOrderSelect = [{ return 1 + MF.getTarget().getSubtarget&...

Hi, everyone. I' have three set of registers - read-only regs, general purpose regs (read and write), and write-only regs. How should I partition them into different RegisterClasses so that I can easy define the instruction? All RegisterClasses must be mutally exclusive. That is, a register can only be in a RegisterClass. Otherwise TableGen will raise an error message. def ReadOnlyRegClass : RegisterClass<...>; def GeneralPurposeRegClass : RegisterClass<...&gt...

All registers in my hardware are 4-element vector registers (128-bit). Some are floating point registers, and the others are integer registers. I typedef two packed classes: [4 x float] and [4 x int], and add an enum 'packed' to MVT::ValueType (ValuesTypes.h). I declared all 'RegisterClass'es to be 'packed' (first argument of RegisterClass): def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>; def INT_ReadOnlyRC : RegisterClass<packed, 128, [I0, I1]>; def FP_ReadOnlyRC : RegisterClass<packed, 128, [F0, F1]>; def MOVgg : BinaryInst<...

Hi All, I have a question about TableGen RegisterClass definition. I need to map different size of MVTs into a register class as below. def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...> When I look at TableGen and CodeGen, it looks the types are used as following: 1. MCRegisterClass's RegSize and Alignment 2. SpillSize in...

On 4/12/2018 8:01 AM, Dominique Torette via llvm-dev wrote: > > But there is one small issue in the inference of RegisterClass of the > implicitly defined register. > > As shown below, the %vreg6<def> is implicitly defined as FPUabRegisterClass. > > This register class accepts the v2f32 type, but for others addressing > mode context this register should be FPUabOffsetClass. > > Is there a...

Hello. I've tried to add some simple arithmetic vector operations to the BPF backend available in the LLVM repo. Because I added in BPFRegisterInfo.td another RegisterClass (taken from the Mips backend): def MSA128W: RegisterClass<"BPF", [v2i64, v2f64], 128, (sequence "W%u", 0, 31)>; in order to support vector for example, ADD operations, I get the following error when building llc: JEQ_ri: (BPFbrcc...

On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote: > I' have three set of registers - read-only regs, general purpose regs > (read and write), and write-only regs. How should I partition them > into different RegisterClasses so that I can easy define the > instruction? [snip] > def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest, > GeneralPurposeRegClass :$src), "mov $dest, $src">; > > There can be only one RegisterClass defined for each instruction > operand, but actuall...

...= "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; multiclass BinaryOpMCInt<ILOpCode OpCode,...

...ware are 4-element vector registers (128-bit). > Some are floating point registers, and the others are integer > registers. > > I typedef two packed classes: [4 x float] and [4 x int], and add an > enum 'packed' to MVT::ValueType (ValuesTypes.h). > > I declared all 'RegisterClass'es to be 'packed' (first argument of > RegisterClass): > > def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>; > def INT_ReadOnlyRC : RegisterClass<packed, 128, [I0, I1]>; > def FP_ReadOnlyRC : RegisterClass<packed, 128, [F0, F1]>; ... >...

On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote: > 2005/7/23, Chris Lattner <sabre at nondot.org>: >> What does a 'read only' register mean? Is it a constant (e.g. returns >> 1.0)? Otherwise, how can it be a useful value? > > Yes, it's a constant register. > > Because the instruction cannot contain an immediate value, a constant > value may be stored in

..._TO_REGCLASS t14, TargetConstant:i32<8> t18: v2f32 = INSERT_SUBREG IMPLICIT_DEF:v2f32, t16, TargetConstant:i32<1> t6: v2f32 = INSERT_SUBREG t18, t16, TargetConstant:i32<2> t7: v2f32 = FMUL_AB_oo t2, t6 But there is one small issue in the inference of RegisterClass of the implicitly defined register. As shown below, the %vreg6<def> is implicitly defined as FPUabRegisterClass. This register class accepts the v2f32 type, but for others addressing mode context this register should be FPUabOffsetClass. Is there a mechanism, an option to inforce/control the...

The blow snippet in target.td shows the regList in RegisterClass is typed as dag. Why not make it a simple list, such as list<Register>? class RegisterClass<string namespace, list<ValueType> regTypes, int alignment, dag regList> Thanks, -Thomson -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.l...

2005/7/23, Chris Lattner <sabre at nondot.org>: > > What does a 'read only' register mean? Is it a constant (e.g. returns > 1.0)? Otherwise, how can it be a useful value? Yes, it's a constant register. Because the instruction cannot contain an immediate value, a constant value may be stored in a constant register, and it's defined _before_ the program starts by

...= "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; multiclass BinaryOpMCInt<ILOpCode OpCode,...

...def %Vec4 <1,2,3,4> // v1, v2, c1 are not allowed to be destination register // of any instruction hereafter. %r1 = add %Vec4 v1, c1 %r2 = mul %Vec4 v1, c2 %o1 = mul %Vec4 r2, v2 // write the output register 'o1' I planed to partition the register into different RegisterClass: input, output, general purpose, constant, etc. def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>; def InputRC : RegisterClass<packed, 128, [V0, V1]>; def ConstantRC : RegisterClass<packed, 128, [C0, C1]>; def ADDgg : BinaryInst<0x51, ( ops GeneralPurposeR...

Hi, I'm porting some existing code of mine to CVS HEAD, and don't understand something about new RegisterClass TableGen definition: class RegisterClass<string namespace, list<ValueType> regTypes,........ { ..... string Namespace = namespace; What is this "namespace" thing? It looks like it should contain the name of backend, right? // RegType - Specify the Valu...

Hi All, I'm working on a back end for an architecture that makes use of multi- typed register classes. def MR: RegisterClass<"namespace", [type1, type2, ... ], ... > When running some preliminary tests I found that the instruction selector refused to select certain ops (specifically stores) for some instructions when the operand type wasn't the first type for the register class. After some digg...

...List = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; > multiclass BinaryOp...

...def R0 : TempReg<0, "r0">; def R32 : TempReg<31, "r32">; def V0 : InputReg<0, "v0">; .. def V10 : InputReg<9, "v10">; def O0 : OutputReg<0, "o0">; .. def O4 : OutputReg<4, "o4">; def FloatingPointRC : RegisterClass<packed, 128, [R0, R1, R2, ..., R32, C0, C1, ..., C200, V0, ..., V10, O1, O2, O3, O4]> { let Methods = [{ iterator allocation_order_end(MachineFunction &MF) const { return end()-(4+10+200); // only TempReg can be allocated }]; } def IntegerRC : Reg...

...v' register-to-register copy instruction will be coallesced and eliminated by the register allocator. The regalloc will eliminate the virtual registers, assigning physical GPRs. This is what the 'allocation order' is to cover. > I planed to partition the register into different RegisterClass: > input, output, general purpose, constant, etc. > > def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>; > def InputRC : RegisterClass<packed, 128, [V0, V1]>; > def ConstantRC : RegisterClass<packed, 128, [C0, C1]>; The way you want to partition these...