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vaddv32i16
2019 Jul 18
2
Question about TableGen RegisterClass definition
Hi All,
I have a question about TableGen RegisterClass definition.
I need to map different size of MVTs into a register class as below.
def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>
When I look at TableGen and CodeGen, it looks the types are used as following:
1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction