Displaying 5 results from an estimated 5 matches for "v32i16".
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v2i16
2020 Jun 25
2
How to implement load/store for vector predicate register
....
The hardware has 64 vector registers(vr for short) and 8 vector predicate registers. And there is no move instructions between vr and vpr.
vr supports many operations, and vpr supports vpror, vprxor, vprand and vprinv operations.
A vr has 512 bits, and a vpr has 128 bits. vr is used for v16i32, v32i16, v64i8. And a scalar register has 32 bits.
If we compare or add two v16i32, a element in vpr has 8 bits. If we compare or add two v64i8, then a element in vpr has 2 bits(one bit for compare flag and one bit for carry flag).
A element in vpr contains carry flag and compare flag.
We have defined re...
2020 Jun 26
2
How to implement load/store for vector predicate register
....
The hardware has 64 vector registers(vr for short) and 8 vector predicate registers. And there is no move instructions between vr and vpr.
vr supports many operations, and vpr supports vpror, vprxor, vprand and vprinv operations.
A vr has 512 bits, and a vpr has 128 bits. vr is used for v16i32, v32i16, v64i8. And a scalar register has 32 bits.
If we compare or add two v16i32, a element in vpr has 8 bits. If we compare or add two v64i8, then a element in vpr has 2 bits(one bit for compare flag and one bit for carry flag).
A element in vpr contains carry flag and compare flag.
We have defined re...
2019 Jul 18
2
Question about TableGen RegisterClass definition
Hi All,
I have a question about TableGen RegisterClass definition.
I need to map different size of MVTs into a register class as below.
def TestReg : RegisterClass<"Test", [v8i32, v4i32], ...>
When I look at TableGen and CodeGen, it looks the types are used as following:
1. MCRegisterClass's RegSize and Alignment
2. SpillSize in TableGen
3. Type constraint for instruction
2016 Mar 18
2
Immediate operand for load instruction, in back end
...string AsmString = !strconcat("mov $wd, ($addrsrc)");
list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addrsrc)))];
InstrItinClass Itinerary = itin;
string DecoderMethod = "DecodeMSA128Mem";
}
class LD_D_DESC : LD_DESC_BASE<"ldvd", load, v32i16, MSA128DOpnd>;
I've tried to change mem_msa to hold only let MIOperandInfo = (ops simm10) but there
are problems it seems:
// MSA specific address operand
def mem_msa : mem_generic {
let MIOperandInfo = (ops ptr_rc, simm10);
let EncoderMethod = "getMSAMemEncoding";
}...
2016 Mar 22
0
Immediate operand for load instruction, in back end
...cat("mov $wd, ($addrsrc)");
> list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addrsrc)))];
> InstrItinClass Itinerary = itin;
> string DecoderMethod = "DecodeMSA128Mem";
> }
>
> class LD_D_DESC : LD_DESC_BASE<"ldvd", load, v32i16, MSA128DOpnd>;
>
>
> I've tried to change mem_msa to hold only let MIOperandInfo = (ops
> simm10) but there
> are problems it seems:
>
> // MSA specific address operand
> def mem_msa : mem_generic {
> let MIOperandInfo = (ops ptr_rc, simm10);
> let Encode...