llvm dev - Sep 2017 - Describing subreg load for vectors without using vector_insert

Hi,

We are using a vector_insert in our target, to describe an instruction
performing a lane-load of a vector register as:

set $dstReg, (vector_insert $dstReg, (load $addr)), imm:$lane)

However, this means that the dstReg is also marked as used in the
instruction, which we do not want. We can do a direct lane-load to a part
of the vector register without disturbing the rest, and hence would like to
do a subregister-load.

Is there a way to achieve that?

Best regards
Saurabh
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It would appear that what you're after here is the ability to specify defs
and uses of parts of registers. Namely, you'd like to model the fact that
loading into one lane of a register redefines only that lane and
instructions that use other lanes need not be concerned with that.

I believe that there is no way to model this using subregisters only. A def
of a subregister is a def of the super register since it certainly does
modify that register.
If I'm not mistaken, the only way you'd be able to model such a setup is
to
have separate register classes for the lanes that can be defined/used
separately. The registers in those classes can then be subregisters of the
full vector register. In this way, single-lane defs affect users of that
lane and users of the full vector register.
However, there was some work recently to allow parameterized register
classes, so this may be simpler to accomplish now.

I'm not sure there are targets that you can use for examples of how to
accomplish this. I work on PPC where our floating point values go into one
lane of vector registers. However, there is no way in the ISA to use the
other part of the vector register, so we don't model that. But this at
least gives you half of the story. You can look at PPC's VSRC/VSFRC
register classes. What you would add is register classes for all the lanes.
Then instructions that use a single lane would use a register from the
appropriate class.

This may not be what you're after at all, in which case I hope at least
some of this is helpful in some way.

Nemanja


On Tue, Sep 19, 2017 at 5:26 PM, Saurabh Verma via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi,
>
> We are using a vector_insert in our target, to describe an instruction
> performing a lane-load of a vector register as:
>
> set $dstReg, (vector_insert $dstReg, (load $addr)), imm:$lane)
>
> However, this means that the dstReg is also marked as used in the
> instruction, which we do not want. We can do a direct lane-load to a part
> of the vector register without disturbing the rest, and hence would like to
> do a subregister-load.
>
> Is there a way to achieve that?
>
> Best regards
> Saurabh
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
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