Displaying 6 results from an estimated 6 matches for "vector_insert".
2017 Sep 19
1
Describing subreg load for vectors without using vector_insert
Hi,
We are using a vector_insert in our target, to describe an instruction
performing a lane-load of a vector register as:
set $dstReg, (vector_insert $dstReg, (load $addr)), imm:$lane)
However, this means that the dstReg is also marked as used in the
instruction, which we do not want. We can do a direct lane-load to a part
of t...
2009 Dec 02
1
[LLVMdev] More AVX Advice Needed
...struction for ISel; it's used inside
> the custom lowering for INSERT_VECTOR_ELT and VECTOR_SHUFFLE.
Yes, that's how I found out about it. :)
Why not just use ISD::INSERT_VECTOR_ELT?
And what's the difference between vector_extract and extractelt in
TargetSelectionDAG.td? Ditto vector_insert vs. insertelt.
-Dave
2009 Dec 02
0
[LLVMdev] More AVX Advice Needed
On Wed, Dec 2, 2009 at 3:08 PM, David Greene <dag at cray.com> wrote:
> On Wednesday 02 December 2009 16:51, Eli Friedman wrote:
>> On Wed, Dec 2, 2009 at 2:44 PM, David Greene <dag at cray.com> wrote:
>> > I'm working on some of the AVX insert/extract instructions. They're
>> > stupid. They do not operate on ymm registers, meaning we have to
2009 Dec 02
2
[LLVMdev] More AVX Advice Needed
On Wednesday 02 December 2009 16:51, Eli Friedman wrote:
> On Wed, Dec 2, 2009 at 2:44 PM, David Greene <dag at cray.com> wrote:
> > I'm working on some of the AVX insert/extract instructions. They're
> > stupid. They do not operate on ymm registers, meaning we have to
> > use VINSERTF128/VEXTRACTF128 and then do the real operation.
> >
> > Anyway,
2019 Nov 28
2
Question on pattern matching extractelt
Hi,
I have an issue with pattern matching.
I have the following SelectionDAG:
t13: i32 = extract_vector_elt t2, Constant:i64<1>
That I am trying to match with the following pattern:
def : Pat<(extractelt (v4i16 SingleReg:$v), 1), (SRADd1 SingleReg :$v, (i64 16))>;
But for some reason the pattern does not match.
It seems to be due to the fact extract_vector_elt's result
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...gt;;
> +
> +/* Insert element pattern */
> +class Insert_Element <ValueType elem_type, ValueType vec_type,
> + RegisterClass elem_class, RegisterClass vec_class,
> + int sub_idx, SubRegIndex sub_reg> : Pat <
> +
> + (vec_type (vector_insert (vec_type vec_class:$vec),
> + (elem_type elem_class:$elem), sub_idx)),
> + (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
> +>;
> +
> +// Vector Build pattern
> +class Vector_Build <ValueType vecType, RegisterClass elemClass> : Pat &...