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452384
2017 Sep 19
1
Describing subreg load for vectors without using vector_insert
Hi,
We are using a vector_insert in our target, to describe an instruction
performing a lane-load of a vector register as:
set $dstReg, (vector_insert $dstReg, (load $addr)), imm:$lane)
However, this means that the dstReg is also marked as used in the
instruction, which we do not want. We can do a direct lane-load to a part
of the vector register without disturbing the rest, and hence would