search for: dstreg

On Sep 5, 2014, at 10:21 AM, Juergen Ributzka <juergen at apple.com> wrote: > clearKillFlags seems a little "overkill" to me. In this case you could just simply transfer the value of the kill flag from the SrcReg to the DstReg. We are extending the live-range of SrcReg. I do not see how you could relate that to the kill flag of DstReg. Therefore, I still think, this is the right fix. -Quentin > > -Juergen > > On 09/05/14, Quentin Colombet <qcolombet at apple.com> wrote: >> >> Hi Patri...

Hello, I'm writing a backend for an architecture that only has LOAD Instructions that first copy the old value of the target register in another register and after that load the provided value into the register. Example of an addition: load a, reg1; // -> copies old value of reg1 in reg2 and loads value from a into reg1 load b, reg1; // -> copies old value of reg1 in reg2 and loads

Hi, We are using a vector_insert in our target, to describe an instruction performing a lane-load of a vector register as: set $dstReg, (vector_insert $dstReg, (load $addr)), imm:$lane) However, this means that the dstReg is also marked as used in the instruction, which we do not want. We can do a direct lane-load to a part of the vector register without disturbing the rest, and hence would like to do a subregister-load. Is ther...

Where does the unsignedSub come from? On 2017-02-15 20:38, Ryan Taylor wrote: > Sorry, it should be: > > defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs, > GPRRegs, DSTRegs, i16, i16, i16, uimm16, immZExt16x>; > > On Wed, Feb 15, 2017 at 2:37 PM, Ryan Taylor <ryta1203 at gmail.com> > wrote: > >> I see. If I put simm16 and immSExt16x in place of uimm16 and >> immZExt16x >> respectively, the imm matches but it prints out -3276...

On Jun 15, 2010, at 2:48 PM, Jakob Stoklund Olesen wrote: > I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer.

It appears that it's impossible to duplicate a node in the dag. For example, there is some code: b = a * a; // a is a global int A LD node is generated for A and it goes into both Operand 0 and 1 of the MUL node. The issue is I'm trying to match a pattern of: set dstReg:$dstD (OpNode (srcAType (load addr32:$srcA)), (srcBType (load addr32:$srcB))) so basically a mem, mem, reg operation. The issue is this pattern won't match in the above example because there is only one LD generated for 'a'. I tried to duplicate the LD in the dag but it doesn't s...

...ister class) in the DMFC1 rule for testing. Next, I added the code in ExpandPseudo to use the following pseudo instruction expansion: void MipsExpandPseudo::ExpandCopyF64(MachineBasicBlock& MBB, MachineBasicBlock::iterator I) { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); const MCInstrDesc& Dmfc1Tdd = TII->get(MIPS::DMFC1); DebugLoc dl = I->getDebugLoc(); const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); BuildMI(MBB, I, d...

..."; let OperandType = "OPERAND_IMMEDIATE"; } def immSExt16x : ImmLeaf<i16, [{ return isInt<16>(Imm); }]>; def immZExt16x : ImmLeaf<i16, [{ return isUInt<16>(Imm); }]>; defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs, GPRRegs, DSTRegs, i16, i16, i16, simm16, immZExt16x>; multiclass ABD_NonCommutative<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass srcBReg, RegisterClass dstReg, ValueType srcAType, ValueType srcBType, ValueType dstType, Operand ImmOd, ImmLeaf imm...

Here is the instruction in question: multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass dstReg, ValueType srcAType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, [(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>; def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg,...

I am considering adding a new target independent codegen-only COPY instruction to our MachineInstr representation. It would be used to replace INSERT_SUBREG, EXTRACT_SUBREG, and virtual register copies after instruction selection. Selection DAG still needs {INSERT,EXTRACT}_SUBREG, but they would not appear as MachineInstrs any longer. The COPY instruction handles subreg operations with less

...odeGen/MachineSink.cpp index 7782001..261af54 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -157,6 +157,11 @@ bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr *MI, DEBUG(dbgs() << "*** to: " << *MI); MRI->replaceRegWith(DstReg, SrcReg); MI->eraseFromParent(); + + // Conservatively, clear any kill flags, since it's possible that they are no + // longer correct. + MRI->clearKillFlags(SrcReg); + ++NumCoalesces; return true; } -- 2.1.0 From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs....

...t;qcolombet at apple.com> wrote: > > On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the instruction in question: > > multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass > srcAReg, > RegisterClass dstReg, ValueType srcAType, > ValueType dstType, Operand ImmOd, ImmLeaf imm_type> > { > def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, > [(set dstReg:$dstD, (OpNode > srcAReg:$srcA))]>; > def IMM_REG : SetADInOut<asmstr,...

...> >> >> On Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: >> >> Here is the instruction in question: >> >> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >> srcAReg, >> RegisterClass dstReg, ValueType srcAType, >> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >> { >> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >> [(set dstReg:$dstD, (OpNode >> srcAReg:$srcA))]>; >> def IMM_REG...

...n Aug 25, 2015, at 10:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: >>> >>> Here is the instruction in question: >>> >>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >>> srcAReg, >>> RegisterClass dstReg, ValueType srcAType, >>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >>> { >>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >>> [(set dstReg:$dstD, (OpNode >>> srcAReg:$srcA))]>; >&g...

...ting. > > Next, I added the code in ExpandPseudo to use the following pseudo > instruction expansion: > > void MipsExpandPseudo::ExpandCopyF64(MachineBasicBlock& MBB, > MachineBasicBlock::iterator > I) { > unsigned DstReg = I->getOperand(0).getReg(); > unsigned SrcReg = I->getOperand(1).getReg(); > const MCInstrDesc& Dmfc1Tdd = TII->get(MIPS::DMFC1); > > DebugLoc dl = I->getDebugLoc(); > const uint16_t* SubReg = > TM.getRegisterInfo()->getSubRegisters(SrcR...

...AM, Ryan Taylor <ryta1203 at gmail.com> wrote: >>>> >>>> Here is the instruction in question: >>>> >>>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >>>> srcAReg, >>>> RegisterClass dstReg, ValueType srcAType, >>>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >>>> { >>>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >>>> [(set dstReg:$dstD, (OpNode >>>> srcAReg:...

Hi LLVM, IRBuilder can fold constants (that behaviour can be controlled by Folder type). What do you think about optionally allow IRBuilder to eliminate no-op instructions like `add %a, 0` or `memcpy(%a, %b, 0)`? - Paweł -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150423/4f99a092/attachment.html>

...[0]) > %reg15: [938,942:1 [0]) > > My assumption was that after MergeInClobberRanges that %reg15 > would contain [458,5168:0 [0]). But it doesn't. So this is the call site? // Update the liveintervals of sub-registers. for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS) li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt, li_- >getVNInfoAllocator()); Can you take a look at MergeInClobberRanges() to see what is going on? Otherwise, please file a bug with a test case. Evan &g...

> On Jun 15, 2015, at 7:05 AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > To be more specific: > > We have some operators that we are currently implementing as intrinsics, for example things like: abs, min, max, etc..... > > for some code: > > int a; > > int food() > { > return abs(a); > } > > the corresponding operator should

...MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); + + MVT PVT = getPointerTy(MF->getDataLayout()); + unsigned PtrSize = PVT.getStoreSize(); + assert(PVT == MVT::i32 && "Invalid Pointer Size!"); + + // Need to "fix-up" this value later. + unsigned DstReg = MI->getOperand(0).getReg(); + const TargetRegisterClass *RC = MRI.getRegClass(DstReg); + assert(RC->hasType(MVT::i32) && "Invalid destination!"); + unsigned mainDstReg = MRI.createVirtualRegister(RC); + unsigned restoreDstReg = MRI.createVirtualRegister(RC); + +...