Displaying 5 results from an estimated 5 matches for "vsfrc".
2017 May 30
2
Pseudo-instruction that overwrites its input register
...of the NoEncode examples in PPCInstrInfo.td seem to have an
isel pattern; and the VSX examples, like XSMADDADP, seem to match on
setting a single output:
let BaseName = "XSMADDADP" in {
let isCommutable = 1 in
def XSMADDADP : XX3Form<60, 33,
(outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
"xsmaddadp $XT, $XA, $XB", IIC_VecFP,
[(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>,
RegConstraint<"$XTi = $XT">, NoEncode<"$XTi&q...
2017 May 28
2
Pseudo-instruction that overwrites its input register
On Sun, 28 May 2017, David Chisnall wrote:
>> let Constraints = "@earlyclobber $reg" in
>> def LDWRdPtr : Pseudo<(outs DREGS:$reg),
>> (ins PTRREGS:$ptrreg),
>> "ldw\t$reg, $ptrreg",
>> [(set i16:$reg, (load i16:$ptrreg))]>,
>>
2017 May 30
1
Pseudo-instruction that overwrites its input register
...PPCInstrInfo.td seem to have an
> isel pattern; and the VSX examples, like XSMADDADP, seem to match on
> setting a single output:
>
> let BaseName = "XSMADDADP" in {
> let isCommutable = 1 in
> def XSMADDADP : XX3Form<60, 33,
> (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA,
> vsfrc:$XB),
> "xsmaddadp $XT, $XA, $XB", IIC_VecFP,
> [(set f64:$XT, (fma f64:$XA, f64:$XB,
> f64:$XTi))]>,
> RegConstraint<"$XTi = $XT">, No...
2017 Sep 19
1
Describing subreg load for vectors without using vector_insert
Hi,
We are using a vector_insert in our target, to describe an instruction
performing a lane-load of a vector register as:
set $dstReg, (vector_insert $dstReg, (load $addr)), imm:$lane)
However, this means that the dstReg is also marked as used in the
instruction, which we do not want. We can do a direct lane-load to a part
of the vector register without disturbing the rest, and hence would
2019 Aug 20
2
Spills on second bank of registers
Hi Tim,
I wonder if you could help me with the following, even if just giving some pointers about where to look. I previously posted a similar question in the mailing list, but unfortunately I have not received a reply. This is the subject:
I want to reduce the number of register spills to the stack that are created around storeRegToStackSlot and loadRegFromStackSlot
In order to do so, I can