I think that what I did originally should have worked and the bug was correct as I reported it. Here is an alternate implementation which has the same problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>; I think that the problem has to do with the operaand lists not working if there is substitution required. Tablegen is only complaining about $rx, $ry and $rz . On 07/03/2012 05:35 PM, Sean Silva wrote:> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, > InstrItinClass itin> : // ... > > This class has template args. You don't specify them in the first > template arg of > class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... > > --Sean Silva > > On Tue, Jul 3, 2012 at 2:29 PM, reed kotler<rkotler at mips.com> wrote: >> Not sure what you mean. >> >> I.OutOperandList == (outs CPU16Regs:$rx) >> >> I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) >> >> >> >> >> On 07/02/2012 09:26 PM, Sean Silva wrote: >>> I think you're missing the template args for `FRRR16_ins` in the first >>> argument. The switch in TGParser::ParseType() doesn't cover the case >>> of types with template args though... which makes me wonder what is >>> going on inside of TableGen to make `I.f` and `I.AsmString` valid... >>> >>> --Sean Silva >>> >>> On Mon, Jul 2, 2012 at 8:07 PM, reed kotler<rkotler at mips.com> wrote: >>>> I've filed the following bug. Maybe I'm doing something stupid here or >>>> maybe someone knows of a workaround. >>>> >>>> The following fragment from mips16 (not yet checked into main source). >>>> >>>> The problem is that I should be able to pass parameters: >>>> I.OutOperandList, I.InOperandList >>>> >>>> But instead, I must back substitute what I know the values of these are. >>>> (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) >>>> >>>> >>>> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, >>>> InstrItinClass itin> : >>>> FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, >>>> CPU16Regs:$ry), >>>> !strconcat(asmstr, "\t$rz, $rx, $ry"), >>>> pattern, itin>; >>>> >>>> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: >>>> FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), >>>> // tablegen bug: should be I.OutOperandList, >>>> I.InOperandList, >>>> I.AsmString, >>>> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], >>>> I.Itinerary> { >>>> let isCommutable = isComm; >>>> let isReMaterializable = 1; >>>> } >>>> _______________________________________________ >>>> LLVM Developers mailing list >>>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >>
This variant works: class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } On 07/05/2012 03:11 PM, reed kotler wrote:> I think that what I did originally should have worked and the bug was > correct as I reported it. > > Here is an alternate implementation which has the same problem. > > class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: > FRRR16<!cast<FRRR16_ins>(I).f, > !cast<FRRR16_ins>(I).OutOperandList, > !cast<FRRR16_ins>(I).InOperandList, > !cast<FRRR16_ins>(I).AsmString, > [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], > !cast<FRRR16_ins>(I).Itinerary> { > let isCommutable = isComm; > let isReMaterializable = 1; > } > > def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>; > > I think that the problem has to do with the operaand lists not working > if there is substitution > required. > > Tablegen is only complaining about $rx, $ry and $rz . > > On 07/03/2012 05:35 PM, Sean Silva wrote: >> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, >> InstrItinClass itin> : // ... >> >> This class has template args. You don't specify them in the first >> template arg of >> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... >> >> --Sean Silva >> >> On Tue, Jul 3, 2012 at 2:29 PM, reed kotler<rkotler at mips.com> wrote: >>> Not sure what you mean. >>> >>> I.OutOperandList == (outs CPU16Regs:$rx) >>> >>> I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) >>> >>> >>> >>> >>> On 07/02/2012 09:26 PM, Sean Silva wrote: >>>> I think you're missing the template args for `FRRR16_ins` in the first >>>> argument. The switch in TGParser::ParseType() doesn't cover the case >>>> of types with template args though... which makes me wonder what is >>>> going on inside of TableGen to make `I.f` and `I.AsmString` valid... >>>> >>>> --Sean Silva >>>> >>>> On Mon, Jul 2, 2012 at 8:07 PM, reed kotler<rkotler at mips.com> wrote: >>>>> I've filed the following bug. Maybe I'm doing something stupid here or >>>>> maybe someone knows of a workaround. >>>>> >>>>> The following fragment from mips16 (not yet checked into main source). >>>>> >>>>> The problem is that I should be able to pass parameters: >>>>> I.OutOperandList, I.InOperandList >>>>> >>>>> But instead, I must back substitute what I know the values of these are. >>>>> (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) >>>>> >>>>> >>>>> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, >>>>> InstrItinClass itin> : >>>>> FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, >>>>> CPU16Regs:$ry), >>>>> !strconcat(asmstr, "\t$rz, $rx, $ry"), >>>>> pattern, itin>; >>>>> >>>>> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: >>>>> FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), >>>>> // tablegen bug: should be I.OutOperandList, >>>>> I.InOperandList, >>>>> I.AsmString, >>>>> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], >>>>> I.Itinerary> { >>>>> let isCommutable = isComm; >>>>> let isReMaterializable = 1; >>>>> } >>>>> _______________________________________________ >>>>> LLVM Developers mailing list >>>>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Please include a complete (and preferably minimal) testcase exhibiting the behavior. It is difficult to help you when all you provide is a narrow window of what is going on. --Sean Silva On Thu, Jul 5, 2012 at 3:29 PM, reed kotler <rkotler at mips.com> wrote:> This variant works: > > > class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: > FRRR16<!cast<FRRR16_ins>(I).f, > (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), > // !cast<FRRR16_ins>(I).OutOperandList, > // !cast<FRRR16_ins>(I).InOperandList, > > !cast<FRRR16_ins>(I).AsmString, > [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], > !cast<FRRR16_ins>(I).Itinerary > { > let isCommutable = isComm; > let isReMaterializable = 1; > } > > On 07/05/2012 03:11 PM, reed kotler wrote: >> >> I think that what I did originally should have worked and the bug was >> correct as I reported it. >> >> Here is an alternate implementation which has the same problem. >> >> class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: >> FRRR16<!cast<FRRR16_ins>(I).f, >> !cast<FRRR16_ins>(I).OutOperandList, >> !cast<FRRR16_ins>(I).InOperandList, >> !cast<FRRR16_ins>(I).AsmString, >> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], >> !cast<FRRR16_ins>(I).Itinerary> { >> let isCommutable = isComm; >> let isReMaterializable = 1; >> } >> >> def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>; >> >> I think that the problem has to do with the operaand lists not working >> if there is substitution >> required. >> >> Tablegen is only complaining about $rx, $ry and $rz . >> >> On 07/03/2012 05:35 PM, Sean Silva wrote: >>> >>> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, >>> InstrItinClass itin> : // ... >>> >>> This class has template args. You don't specify them in the first >>> template arg of >>> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... >>> >>> --Sean Silva >>> >>> On Tue, Jul 3, 2012 at 2:29 PM, reed kotler<rkotler at mips.com> wrote: >>>> >>>> Not sure what you mean. >>>> >>>> I.OutOperandList == (outs CPU16Regs:$rx) >>>> >>>> I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) >>>> >>>> >>>> >>>> >>>> On 07/02/2012 09:26 PM, Sean Silva wrote: >>>>> >>>>> I think you're missing the template args for `FRRR16_ins` in the first >>>>> argument. The switch in TGParser::ParseType() doesn't cover the case >>>>> of types with template args though... which makes me wonder what is >>>>> going on inside of TableGen to make `I.f` and `I.AsmString` valid... >>>>> >>>>> --Sean Silva >>>>> >>>>> On Mon, Jul 2, 2012 at 8:07 PM, reed kotler<rkotler at mips.com> wrote: >>>>>> >>>>>> I've filed the following bug. Maybe I'm doing something stupid here or >>>>>> maybe someone knows of a workaround. >>>>>> >>>>>> The following fragment from mips16 (not yet checked into main source). >>>>>> >>>>>> The problem is that I should be able to pass parameters: >>>>>> I.OutOperandList, I.InOperandList >>>>>> >>>>>> But instead, I must back substitute what I know the values of these >>>>>> are. >>>>>> (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) >>>>>> >>>>>> >>>>>> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, >>>>>> InstrItinClass itin> : >>>>>> FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, >>>>>> CPU16Regs:$ry), >>>>>> !strconcat(asmstr, "\t$rz, $rx, $ry"), >>>>>> pattern, itin>; >>>>>> >>>>>> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: >>>>>> FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, >>>>>> CPU16Regs:$rz), >>>>>> // tablegen bug: should be I.OutOperandList, >>>>>> I.InOperandList, >>>>>> I.AsmString, >>>>>> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], >>>>>> I.Itinerary> { >>>>>> let isCommutable = isComm; >>>>>> let isReMaterializable = 1; >>>>>> } >>>>>> _______________________________________________ >>>>>> LLVM Developers mailing list >>>>>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > >