search for: cpu16reg

Not sure what you mean. I.OutOperandList == (outs CPU16Regs:$rx) I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) On 07/02/2012 09:26 PM, Sean Silva wrote: > I think you're missing the template args for `FRRR16_ins` in the first > argument. The switch in TGParser::ParseType() doesn't cover the case > of types with template args th...

...ame problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>; I think that the problem has to do with the operaand lists not...

...ng stupid here or maybe someone knows of a workaround. The following fragment from mips16 (not yet checked into main source). The problem is that I should be able to pass parameters: I.OutOperandList, I.InOperandList But instead, I must back substitute what I know the values of these are. (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry), !strconcat(asmstr, "\t$rz, $rx, $ry"),...

This variant works: class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR...

...rgs. You don't specify them in the first template arg of class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... --Sean Silva On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote: > Not sure what you mean. > > I.OutOperandList == (outs CPU16Regs:$rx) > > I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) > > > > > On 07/02/2012 09:26 PM, Sean Silva wrote: >> >> I think you're missing the template args for `FRRR16_ins` in the first >> argument. The switch in TGParser::ParseType() doesn't co...

...s of a workaround. > > The following fragment from mips16 (not yet checked into main source). > > The problem is that I should be able to pass parameters: > I.OutOperandList, I.InOperandList > > But instead, I must back substitute what I know the values of these are. > (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) > > > class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, > InstrItinClass itin> : > FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, > CPU16Regs:$ry), > !strconcat(asmstr,...

...except at the boundary condition where k==-32768 Then it creates the literal -32769 which cannot be placed in a simple immediate field. That creates a lot of extra code for Mips 16. I had originally written a pattern for setge when the right operand is a constant. def: Mips16Pat <(setge CPU16Regs:$lhs, immZExt16:$rhs), (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), (LiRxImmX16 1))>; I was able to work around this boundary case by doing the reverse transformation at the boundary. i..e. z = (x > (k-1)) => z = (x >= k) def: Mips16Pat <(setgt CPU1...

...0b10010, "mflo", IIAlu> { let Uses = [LO]; let neverHasSideEffects = 1; } // // Pseudo Instruction for mult // def MultRxRy16: FMULT16_ins<"mult", IIAlu> { let isCommutable = 1; let neverHasSideEffects = 1; let Defs = [HI, LO]; } def: Mips16Pattern<(mul CPU16Regs:$l, CPU16Regs:$r), [(MultRxRyRz16 CPU16Regs:$l, CPU16Regs:$r), (Mflo16) ]>; Without the list of instructions feature in the Pattern class, I am forced to make a pseudo that has both the mul and mflo instruction in it. This is a very simple example and some, like for example the...

What have you tried? On Sun, Sep 16, 2012 at 3:34 PM, Kotler, Reed <rkotler at mips.com> wrote: > This Pattern class says it's possible but seems just to not work or maybe I'm using it incorrectly. > > Probably I will go and fix it when I'm done with mips16. > > > ________________________________________ > From: Hal Finkel [hfinkel at anl.gov] > Sent:

This Pattern class says it's possible but seems just to not work or maybe I'm using it incorrectly. Probably I will go and fix it when I'm done with mips16. ________________________________________ From: Hal Finkel [hfinkel at anl.gov] Sent: Sunday, September 16, 2012 10:59 AM To: Anton Korobeynikov Cc: Kotler, Reed; LLVM-Dev ‎[llvmdev at cs.uiuc.edu]‎ Subject: Re: [LLVMdev] Pattern

Does anyone understand the purpose of this target inpdendent function? By adding a new register class that is for MIPS16 but not even referencing it, the compiler breaks because of this code. def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add // Return Values and Arguments V0, V1, A0, A1, A2, A3, // Callee save S0, S1 )>; I'm trying to understand how the Arm compiler avoids this problem. But still, what is the logic here? Tia. Reed

Hello, why LLVM does not define physical register limits for MIPS by overriding the TargetRegisterInfo::getRegPressureLimit function the way it’s done for X86 in x86RegisterInfo.cpp and ARM. Thanks in advance. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120818/a8e4f353/attachment.html>