Displaying 20 results from an estimated 66 matches for "outoperandlist".
2012 Jul 05
2
[LLVMdev] bug in tablegen?
...did originally should have worked and the bug was
correct as I reported it.
Here is an alternate implementation which has the same problem.
class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>:
FRRR16<!cast<FRRR16_ins>(I).f,
!cast<FRRR16_ins>(I).OutOperandList,
!cast<FRRR16_ins>(I).InOperandList,
!cast<FRRR16_ins>(I).AsmString,
[(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))],
!cast<FRRR16_ins>(I).Itinerary > {
let isCommutable = isComm;
let isReMaterializable = 1;
}
def foo:...
2012 Jul 03
3
[LLVMdev] bug in tablegen?
Not sure what you mean.
I.OutOperandList == (outs CPU16Regs:$rx)
I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz)
On 07/02/2012 09:26 PM, Sean Silva wrote:
> I think you're missing the template args for `FRRR16_ins` in the first
> argument. The switch in TGParser::ParseType() doesn't cover the case
> of types wi...
2019 Apr 26
3
tablegen dag syntax question
What is the difference between these two fragments (taken from two
different tblgen record dumps)?
dag OutOperandList = (outs GPR:$rd);
dag OutOperandList = (outs R2);
The first is from the RISCV backend record dump. There will be a
substitution at some point for $rd. In the second, I'm specifying R2, no
substitution necessary.
If I specify GPR64:R2 or i64:R2 in my Instruction def, rather than just R2,
tbl...
2012 Jul 05
0
[LLVMdev] bug in tablegen?
This variant works:
class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>:
FRRR16<!cast<FRRR16_ins>(I).f,
(outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz),
// !cast<FRRR16_ins>(I).OutOperandList,
// !cast<FRRR16_ins>(I).InOperandList,
!cast<FRRR16_ins>(I).AsmString,
[(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))],
!cast<FRRR16_ins>(I).Itinerary > {
let isCommutable = isComm;
let isReMaterializable = 1;
}
On 07/0...
2012 Jul 04
0
[LLVMdev] bug in tablegen?
...This class has template args. You don't specify them in the first
template arg of
class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
--Sean Silva
On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote:
> Not sure what you mean.
>
> I.OutOperandList == (outs CPU16Regs:$rx)
>
> I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz)
>
>
>
>
> On 07/02/2012 09:26 PM, Sean Silva wrote:
>>
>> I think you're missing the template args for `FRRR16_ins` in the first
>> argument. The switch in TGParser::ParseTy...
2012 Jul 03
2
[LLVMdev] bug in tablegen?
I've filed the following bug. Maybe I'm doing something stupid here or
maybe someone knows of a workaround.
The following fragment from mips16 (not yet checked into main source).
The problem is that I should be able to pass parameters:
I.OutOperandList, I.InOperandList
But instead, I must back substitute what I know the values of these are.
(outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz)
class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
InstrItinClass itin> :
FRRR16<_f, (outs CPU16Regs:$rz),...
2012 Jul 03
0
[LLVMdev] bug in tablegen?
...ips.com> wrote:
> I've filed the following bug. Maybe I'm doing something stupid here or
> maybe someone knows of a workaround.
>
> The following fragment from mips16 (not yet checked into main source).
>
> The problem is that I should be able to pass parameters:
> I.OutOperandList, I.InOperandList
>
> But instead, I must back substitute what I know the values of these are.
> (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz)
>
>
> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
> InstrItinClass itin> :
>...
2014 Mar 13
2
[LLVMdev] Be Careful with Positionally-Encoded Operands (AArch64, Mips, AMDGPU, etc.)
...SMULHxxx {
> > field bits<32> Inst = { 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, Rm{4},
> > Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, Ra{4}, Ra{3}, Ra{2}, Ra{1},
> > Ra{0}, Rn{4}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{4}, Rd{3}, Rd{2},
> > Rd{1}, Rd{0} };
> > ...
> > dag OutOperandList = (outs GPR64:$Rd);
> > dag InOperandList = (ins GPR64:$Rn, GPR64:$Rm);
> > string AsmString = "smulh $Rd, $Rn, $Rm";
> > list<dag> Pattern = [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))];
> > ...
> > bits<5> Rd = { ?, ?, ?, ?, ? };
> >...
2014 Mar 13
5
[LLVMdev] Be Careful with Positionally-Encoded Operands (AArch64, Mips, AMDGPU, etc.)
...;s an example:
AArch64 has the following instruction definition:
SMULHxxx {
field bits<32> Inst = { 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, Rm{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, Ra{4}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rn{4}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{4}, Rd{3}, Rd{2}, Rd{1}, Rd{0} };
...
dag OutOperandList = (outs GPR64:$Rd);
dag InOperandList = (ins GPR64:$Rn, GPR64:$Rm);
string AsmString = "smulh $Rd, $Rn, $Rm";
list<dag> Pattern = [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))];
...
bits<5> Rd = { ?, ?, ?, ?, ? };
bits<5> Rn = { ?, ?, ?, ?, ? };
bits<5> Rm...
2012 Dec 23
5
[LLVMdev] Getting MCInst "ins" and "outs"
...r1
<MCOperand Reg:105> <-- maps to reg sp
<MCOperand Imm:8> <-- maps to immed #8
<MCOperand Imm:14>
<MCOperand Reg:0>
Now, what are the two last operands (that are not actually present in disassembly)? And is it somehow possible to map the operands to OutOperandList/InOperandList found in the td definition?
--
Vladimir Pouzanov
http://www.farcaller.net/
2012 Apr 19
2
[LLVMdev] Tablegen to match a literal in an instruction
...erns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";
dag OutOperandList = outs;
dag InOperandList = ins;
ILOpCode operation = op;
let Pattern = pattern;
let AsmString = !strconcat(asmstr, "\n");
bit hasIEEEFlag = 0;
bit hasZeroOpFlag = 0;
}
class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg,
RegisterClass sReg...
2012 Apr 19
3
[LLVMdev] Tablegen to match a literal in an instruction
...erns.
What I am trying to do is take a register/register pattern and change it to a register/immediate.
So for example, I have this pattern:
class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMDIL";
dag OutOperandList = outs;
dag InOperandList = ins;
ILOpCode operation = op;
let Pattern = pattern;
let AsmString = !strconcat(asmstr, "\n");
bit hasIEEEFlag = 0;
bit hasZeroOpFlag = 0;
}
class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg,
RegisterClass sReg...
2011 Jan 22
3
[LLVMdev] Question about porting LLVM - code selection without assembler feature
...uot;. I am wondering to know whether I can ignore the
Inst field in the following example:
class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instruction {
field bits<32> Inst;
let Namespace = "SP";
bits<2> op;
let Inst{31-30} = op;
dag OutOperandList = outs;
dag InOperandList = ins;
let AsmString = asmstr;
let Pattern = pattern;
}
And define the instruction class of ported target as:
class Instxxx<dag outs, dag ins, string asmstr, list<dag> pattern> :
Instruction {
let Namespace = "xxx";
dag OutOperandList =...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...o do is take a register/register pattern and change it to a register/immediate.
> So for example, I have this pattern:
> class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
> : Instruction {
> let Namespace = "AMDIL";
> dag OutOperandList = outs;
> dag InOperandList = ins;
> ILOpCode operation = op;
> let Pattern = pattern;
> let AsmString = !strconcat(asmstr, "\n");
> bit hasIEEEFlag = 0;
> bit hasZeroOpFlag = 0;
> }
> class BinaryOp<ILOpCode op, SDNode OpNode, Regi...
2016 Dec 03
2
Immediate operand for vector instructions
...class MSA_I16_FMT<bits<9> opcode>: MSAInst {
bits<16> s16;
let Inst{31-23} = opcode;
let Inst{26-11} = s16;
}
class REP_1R_DESC_BASE<,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
/* From include/llvm/Target/Target.td:
let OperandType = "OPERAND_IMMEDIATE" in {
...
def i64imm : Operand<i64>; */
dag InOperandList = (ins i64imm:$imm);
string AsmString = "REPEAT_X_TIMES(...
2012 Apr 19
0
[LLVMdev] Tablegen to match a literal in an instruction
...o do is take a register/register pattern and change it to a register/immediate.
> So for example, I have this pattern:
> class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
> : Instruction {
> let Namespace = "AMDIL";
> dag OutOperandList = outs;
> dag InOperandList = ins;
> ILOpCode operation = op;
> let Pattern = pattern;
> let AsmString = !strconcat(asmstr, "\n");
> bit hasIEEEFlag = 0;
> bit hasZeroOpFlag = 0;
> }
> class BinaryOp<ILOpCode op, SDNode OpNode, Regi...
2016 Mar 18
2
Immediate operand for load instruction, in back end
...ch is a relative address with base a certain
register and offset:
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = mem_msa,
ComplexPattern Addr = addrimm10,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins MemOpnd:$addrsrc);
string AsmString = !strconcat("mov $wd, ($addrsrc)");
list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addrsrc)))];
InstrItinClass Itinerary = itin;
string DecoderMethod = "DecodeMSA128Mem&qu...
2016 Dec 02
2
Handling argument for an intrinsic
...jRWQzRVltdDJOQnM/view?usp=sharing
Would it be problematic if I somehow extracted the pointer address arg to
the intrisic from TargetConstant and passed it as MachineOperand to the
MachineInstruction?
Opcode definition (Target/Target.td)
==============
+def PATCHABLE_LOG_CALL : Instruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins unknown:$entry);
+ let AsmString = "# XRay Custom Log.";
+ let usesCustomInserter = 1;
+ let hasSideEffects = 1;
+}
Example IR for the graph above
===========
define i32 @caller() nounwind noinline uwtable
"function-instrument"="xra...
2008 Oct 28
1
[LLVMdev] Accessing InstrFormat.td fields
...en I setup my InstrFormat fields, I added some custom fields specific
for my backend. How do I access these from inside LLVM?
For example:
class InstrFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
: Instruction {
let Namespace = "AMD";
dag OutOperandList = outs;
dag InOperandList = ins;
let Pattern = pattern;
let AsmString = asmstr;
OpCodeModifier ocmod;
}
How do I set/read the ocmod struct from either SelectCode or a separate
phase? Is there an example of this?
Micah Villmow
Systems Engineer
Advanced Technology &...
2012 Jan 20
2
[LLVMdev] Tablegen: How to define a Pattern with multiple result instructions
Hi,
I'm trying to create a Pattern that looks something like this:
def my_inst : Instruction <
let OutOperandList = (outs REG:$dst);
let InOperandList = (ins imm:$src);
let Uses = [R0];
>
def int_my_intrinsic : Intrinsic <
[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []
>;
def : Pattern <
(int_my_intrinsic imm:$a, imm:$b, imm:$c),
[(set R0, (MOV_IMM imm:$a)),
(my_inst (...