Displaying 6 results from an estimated 6 matches for "arithlogicr16".
2012 Jul 03
3
[LLVMdev] bug in tablegen?
...t; pattern,
>> InstrItinClass itin> :
>> FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx,
>> CPU16Regs:$ry),
>> !strconcat(asmstr, "\t$rz, $rx, $ry"),
>> pattern, itin>;
>>
>> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>:
>> FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz),
>> // tablegen bug: should be I.OutOperandList, I.InOperandList,
>> I.AsmString,
>> [(set CPU16Regs:$rx, (OpNode...
2012 Jul 04
0
[LLVMdev] bug in tablegen?
class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
InstrItinClass itin> : // ...
This class has template args. You don't specify them in the first
template arg of
class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
--Sean Silva
On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote:
> Not sure what you mean.
>
> I.OutOperandList == (outs CPU16Regs:$rx)
>
> I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz)
&...
2012 Jul 05
2
[LLVMdev] bug in tablegen?
...t $rx, $ry and $rz .
On 07/03/2012 05:35 PM, Sean Silva wrote:
> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
> InstrItinClass itin> : // ...
>
> This class has template args. You don't specify them in the first
> template arg of
> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
>
> --Sean Silva
>
> On Tue, Jul 3, 2012 at 2:29 PM, reed kotler<rkotler at mips.com> wrote:
>> Not sure what you mean.
>>
>> I.OutOperandList == (outs CPU16Regs:$rx)
>>
>> I.InOperandList =...
2012 Jul 05
0
[LLVMdev] bug in tablegen?
.../03/2012 05:35 PM, Sean Silva wrote:
>> class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
>> InstrItinClass itin> : // ...
>>
>> This class has template args. You don't specify them in the first
>> template arg of
>> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ...
>>
>> --Sean Silva
>>
>> On Tue, Jul 3, 2012 at 2:29 PM, reed kotler<rkotler at mips.com> wrote:
>>> Not sure what you mean.
>>>
>>> I.OutOperandList == (outs CPU16Regs:$rx)
>&g...
2012 Jul 03
2
[LLVMdev] bug in tablegen?
...lass FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern,
InstrItinClass itin> :
FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx,
CPU16Regs:$ry),
!strconcat(asmstr, "\t$rz, $rx, $ry"),
pattern, itin>;
class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>:
FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz),
// tablegen bug: should be I.OutOperandList, I.InOperandList,
I.AsmString,
[(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))],
I.Itin...
2012 Jul 03
0
[LLVMdev] bug in tablegen?
..._f, string asmstr, list<dag> pattern,
> InstrItinClass itin> :
> FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx,
> CPU16Regs:$ry),
> !strconcat(asmstr, "\t$rz, $rx, $ry"),
> pattern, itin>;
>
> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>:
> FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz),
> // tablegen bug: should be I.OutOperandList, I.InOperandList,
> I.AsmString,
> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16...