search for: opnod

...n the below example. Consider FMA3 pattern (simplified). let Constraints = "$src1 = $dst" in { multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, RegisterClass RC, ValueType OpVT, PatFrag mem_frag, SDPatternOperator OpNode = null_frag> { def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), [(set RC:$dst,...

...mespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; multiclass BinaryOpMCInt<...

...mespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1> : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; multiclass BinaryOpMCInt<...

...FMA3 pattern > (simplified). > > let Constraints = "$src1 = $dst" in { > multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, > RegisterClass RC, ValueType OpVT, PatFrag mem_frag, > SDPatternOperator OpNode = null_frag> { > > def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), > (ins RC:$src1, RC:$src2, RC:$src3), > !strconcat(OpcodeStr, > "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), >...

...tOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; > mul...

...tOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1> > : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; > mul...

I think that what I did originally should have worked and the bug was correct as I reported it. Here is an alternate implementation which has the same problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))],...

...dropped. Now having covered that the reason the operands are in the order they are is because the only instruction that doesn't use null_frag is this one defm r213 : fma3s_rm<opc213, !strconcat(OpStr, !strconcat("213", PackTy)), x86memop, RC, OpVT, mem_frag, OpNode> Which specifies the operand order as 213 thus why they are 2, 1, 3 in the pattern. ~Craig On Fri, Nov 16, 2012 at 12:19 AM, Anitha B Gollamudi < anitha.boyapati at gmail.com> wrote: > On 16 November 2012 13:41, Anitha B Gollamudi <anitha.boyapati at gmail.com> > wrote: &g...

This variant works: class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString,...

...There are four banks and the formula to figure out which bank a register is in is just: r%4 Which brings me to tablegen: We've got this in our specialized ArchInstrInfo.td: // r1 = r2 op r3 // class ArithOp_RR< bits<7> op, string instr_asm, SDNode opNode, OperandInfo info, InstrItinClass itin > : FR3< op, (outs info.regClass:$r1), (ins info.regClass:$r2, info.regClass:$r3), instr_asm # "\t\t$r1, $r2, $r3, " # info.sizeStr, [(set info.regClass:$r1, (opNode info.re...

...attern: def generic_load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ return isGenericLoad(dyn_cast<LoadSDNode>(N)); }]>; def ADDRf : ComplexPattern<i32, 2, "SelectADDRf", [frameindex], []>; // Load Memory Operations multiclass LOADm<string asm, PatFrag OpNode, ComplexPattern addr> { def _i32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr), asm, [(set (i32 GPR:$dst), (OpNode addr:$ptr))]>; def _f32 : OneInOneOut<IL_OP_MOV, (outs GPR:$dst), (ins MEM:$ptr), asm, [(set (f32 GPR:$dst), (OpNode addr:$ptr))]&gt...

...e type of instruction. The > current PTX_LOGIC version is for 3-operand instructions. A new multiclass > needs to be created for 2-operand logic instructions. I am trying to add a multiclass for 2-operand logic instructions. For example, multiclass PTX_LOGIC_2OP<string opcstr, SDNode opnode> { def ripreds : InstPTX<(outs Preds:$d), (ins Preds:$a), !strconcat(opcstr, ".pred\t$d, $a"), [(set Preds:$d, (opnode Preds:$a))]>; ... } But the error is still the same. Where else should I look into? Th...

I'm confused about how to specify DAG patterns for a given instruction Here is an example for my target class ALU1_RR<bits<4> subOp, string asmstr, SDNode OpNode> : ALU_RR<subOp, asmstr, [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR:$rB)))]>; def ADD : ALU1_RR<0x0, "l.add", add>; The set operation simply creates a list. The add operation creates a union. So at the end [(set GPR:$rD, (OpNode (i32 GPR:$rA), (i32 GPR...

...tin> : >> FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, >> CPU16Regs:$ry), >> !strconcat(asmstr, "\t$rz, $rx, $ry"), >> pattern, itin>; >> >> class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: >> FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), >> // tablegen bug: should be I.OutOperandList, I.InOperandList, >> I.AsmString, >> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))...

class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : // ... This class has template args. You don't specify them in the first template arg of class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... --Sean Silva On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote: > Not sure what you mean. > > I.OutOperandList == (outs CPU16Regs:$rx) > > I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) > > > > > On 07/...

...pport to PTX backend. I add the line below in PTXInstrInfo.td, defm NOT : PTX_LOGIC<"not", not>; But I get errors below, ------------------------------------------------------------------------------- Included from PTX.td:75: PTXInstrInfo.td:732:10: error: Value 'PTX_LOGIC::opnode' of type 'SDNode' is incompatible with initializer 'not' defm NOT : PTX_LOGIC<"not", not>; ^ llvm[3]: Building PTX.td subtarget information with tblgen Included from PTX.td:75: PTXInstrInfo.td:732:10: error: Value 'PTX_LOGIC::opnode' of type ...

...R1, R2, R3, R4, R5, R6, R7)>; def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; The SP can not be used in general purpose arithmetic instructions, therefore I defined the following classes in MyTargetInstrInfo.td: class T5rr16alu<string opcStr, string altOpcStr, SDNode opNode, bits<4> opcode>: Type5 <opcode, (outs GR16:$rd), (ins GR16:$rn, GR16:$rs), AsmStr< opcStr, altOpcStr, "\t$rn, $rs, $rd">.n, [(set GR16:$rd, (opNode GR16:$rn, GR16:$rs)), (implicit SR)]>; I also have sp...

...https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/MipsMSAInstrInfo.td, look for "def ST_D", etc. Note however that my vector unit has a separate memory space. This is why I defined the vector store like: class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst);...

...ncat on a non-string entity? That is, is there some operation that will let me do this (replace SOME_CONCAT with an appropriate operator): (WARNING! Hacked-up tablegen ahead!) multiclass sse_fp_binop_bitwise_rm<bits<8> opc, string OpcodeStr, SDNode OpNode> { // Vector operation emulating scalar (fp) def FsPSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32: $src2), !strconcat(OpcodeStr, "ps"\t{$src2, $dst|$dst, $src2}"), [(set FR32:$dst, (!SOME_CONCAT("x86f&quo...

...structions. A new multiclass needs to be created for 2-operand logic instructions. </pre> </blockquote> <pre wrap=""><!----> I am trying to add a multiclass for 2-operand logic instructions. For example, multiclass PTX_LOGIC_2OP<string opcstr, SDNode opnode> { def ripreds : InstPTX<(outs Preds:$d), (ins Preds:$a), !strconcat(opcstr, ".pred\t$d, $a"), [(set Preds:$d, (opnode Preds:$a))]>; ... } </pre> </blockquote> The error here is due to the fact tha...