search for: inoperandlist

...as I reported it. Here is an alternate implementation which has the same problem. class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, !cast<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>...

Not sure what you mean. I.OutOperandList == (outs CPU16Regs:$rx) I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) On 07/02/2012 09:26 PM, Sean Silva wrote: > I think you're missing the template args for `FRRR16_ins` in the first > argument. The switch in TGParser::ParseType() doesn't cover the case > of types with template args though... which makes me...

...nt works: class ArithLogicRTest16<string I, SDNode OpNode, bit isComm = 0>: FRRR16<!cast<FRRR16_ins>(I).f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // !cast<FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } On 07/05/2012 03:11 PM, reed kotler wrote: > I think that what...

...them in the first template arg of class ArithLogicR16<FRRR16_ins I, SDNode OpNode, bit isComm = 0>: // ... --Sean Silva On Tue, Jul 3, 2012 at 2:29 PM, reed kotler <rkotler at mips.com> wrote: > Not sure what you mean. > > I.OutOperandList == (outs CPU16Regs:$rx) > > I.InOperandList == (ins CPU16Regs:$ry, CPU16Regs:$rz) > > > > > On 07/02/2012 09:26 PM, Sean Silva wrote: >> >> I think you're missing the template args for `FRRR16_ins` in the first >> argument. The switch in TGParser::ParseType() doesn't cover the case >> of types w...

Hi Alex, On 5 December 2016 at 18:00, Alex Susu <alex.e.susu at gmail.com> wrote: > We can compile it. Note that this is the only compilable code w.r.t. > using i64 or i64imm (in the 2 lines above: "dag InOperandList", "list<dag> > Pattern"). Yeah, you actually want to use "imm": list<dag> Pattern = [(int_repeat_x_times imm:$imm)]; When the table generator sees "i64" it doesn't go looking in the InOperandList to determine that the operand should be an...

I've filed the following bug. Maybe I'm doing something stupid here or maybe someone knows of a workaround. The following fragment from mips16 (not yet checked into main source). The problem is that I should be able to pass parameters: I.OutOperandList, I.InOperandList But instead, I must back substitute what I know the values of these are. (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, InstrItinClass itin> : FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$...

...> I've filed the following bug. Maybe I'm doing something stupid here or > maybe someone knows of a workaround. > > The following fragment from mips16 (not yet checked into main source). > > The problem is that I should be able to pass parameters: > I.OutOperandList, I.InOperandList > > But instead, I must back substitute what I know the values of these are. > (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz) > > > class FRRR16_ins<bits<2> _f, string asmstr, list<dag> pattern, > InstrItinClass itin> : > FRRR16<_f, (o...

...{ 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, Rm{4}, > > Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, Ra{4}, Ra{3}, Ra{2}, Ra{1}, > > Ra{0}, Rn{4}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{4}, Rd{3}, Rd{2}, > > Rd{1}, Rd{0} }; > > ... > > dag OutOperandList = (outs GPR64:$Rd); > > dag InOperandList = (ins GPR64:$Rn, GPR64:$Rm); > > string AsmString = "smulh $Rd, $Rn, $Rm"; > > list<dag> Pattern = [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))]; > > ... > > bits<5> Rd = { ?, ?, ?, ?, ? }; > > bits<5> Rn = { ?, ?, ?, ?, ? }; > &gt...

...instruction definition: SMULHxxx { field bits<32> Inst = { 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, Rm{4}, Rm{3}, Rm{2}, Rm{1}, Rm{0}, 0, Ra{4}, Ra{3}, Ra{2}, Ra{1}, Ra{0}, Rn{4}, Rn{3}, Rn{2}, Rn{1}, Rn{0}, Rd{4}, Rd{3}, Rd{2}, Rd{1}, Rd{0} }; ... dag OutOperandList = (outs GPR64:$Rd); dag InOperandList = (ins GPR64:$Rn, GPR64:$Rm); string AsmString = "smulh $Rd, $Rn, $Rm"; list<dag> Pattern = [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))]; ... bits<5> Rd = { ?, ?, ?, ?, ? }; bits<5> Rn = { ?, ?, ?, ?, ? }; bits<5> Rm = { ?, ?, ?, ?, ? }; bits<5> Ra...

...InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); /* From include/llvm/Target/Target.td: let OperandType = "OPERAND_IMMEDIATE" in { ... def i64imm : Operand<i64>; */ dag InOperandList = (ins i64imm:$imm); string AsmString = "REPEAT_X_TIMES($imm"; list<dag> Pattern = [(int_repeat_x_times i64imm:$imm)]; InstrItinClass Itinerary = itin; } class REP_D_DESC : REP_1R_DESC_BASE; class REP_D_ENC : MSA_I16_FMT&...

...rand Reg:105> <-- maps to reg sp <MCOperand Imm:8> <-- maps to immed #8 <MCOperand Imm:14> <MCOperand Reg:0> Now, what are the two last operands (that are not actually present in disassembly)? And is it somehow possible to map the operands to OutOperandList/InOperandList found in the td definition? -- Vladimir Pouzanov http://www.farcaller.net/

...take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1>...

I saw many definitions derived from Instruction defines OutputOperandList and InputOperandList (usually in the xxxInstrFormats.td), but I don't see where they are referenced. Anything I missed here? Thanks, -Thomson -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140112/e6e87e9f/attachment.html>

...take a register/register pattern and change it to a register/immediate. So for example, I have this pattern: class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; ILOpCode operation = op; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); bit hasIEEEFlag = 0; bit hasZeroOpFlag = 0; } class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1>...

...whether I can ignore the Inst field in the following example: class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<32> Inst; let Namespace = "SP"; bits<2> op; let Inst{31-30} = op; dag OutOperandList = outs; dag InOperandList = ins; let AsmString = asmstr; let Pattern = pattern; } And define the instruction class of ported target as: class Instxxx<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "xxx"; dag OutOperandList = outs; dag InOperandList =...

...ern and change it to a register/immediate. > So for example, I have this pattern: > class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> > : Instruction { > let Namespace = "AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterC...

...ern and change it to a register/immediate. > So for example, I have this pattern: > class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern> > : Instruction { > let Namespace = "AMDIL"; > dag OutOperandList = outs; > dag InOperandList = ins; > ILOpCode operation = op; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > bit hasIEEEFlag = 0; > bit hasZeroOpFlag = 0; > } > class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg, > RegisterC...

...ain register and offset: class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs ROWD:$wd); dag InOperandList = (ins MemOpnd:$addrsrc); string AsmString = !strconcat("mov $wd, ($addrsrc)"); list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addrsrc)))]; InstrItinClass Itinerary = itin; string DecoderMethod = "DecodeMSA128Mem"; } class LD_D_DESC : LD_DESC_BASE&l...

...g Would it be problematic if I somehow extracted the pointer address arg to the intrisic from TargetConstant and passed it as MachineOperand to the MachineInstruction? Opcode definition (Target/Target.td) ============== +def PATCHABLE_LOG_CALL : Instruction { + let OutOperandList = (outs); + let InOperandList = (ins unknown:$entry); + let AsmString = "# XRay Custom Log."; + let usesCustomInserter = 1; + let hasSideEffects = 1; +} Example IR for the graph above =========== define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" { %logentryp...

..., I added some custom fields specific for my backend. How do I access these from inside LLVM? For example: class InstrFormat<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { let Namespace = "AMD"; dag OutOperandList = outs; dag InOperandList = ins; let Pattern = pattern; let AsmString = asmstr; OpCodeModifier ocmod; } How do I set/read the ocmod struct from either SelectCode or a separate phase? Is there an example of this? Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro De...