search for: isrematerializable

...<FRRR16_ins>(I).OutOperandList, !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } def foo: ArithLogicRTest16<"AdduRxRyRz16", add, 1>; I think that the problem has to do with the operaand lists not working if there is substitution required. Tablegen is only complaining about $rx, $ry and $rz . On 07/03/2012 05:35 PM, Sean Silva wrote: > class FRRR16...

...t;FRRR16_ins>(I).OutOperandList, // !cast<FRRR16_ins>(I).InOperandList, !cast<FRRR16_ins>(I).AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], !cast<FRRR16_ins>(I).Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; } On 07/05/2012 03:11 PM, reed kotler wrote: > I think that what I did originally should have worked and the bug was > correct as I reported it. > > Here is an alternate implementation which has the same problem. > > class ArithLogicRTest16<string I, SDNode OpNode, bit is...

...$ry, CPU16Regs:$rz), >> // tablegen bug: should be I.OutOperandList, I.InOperandList, >> I.AsmString, >> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], >> I.Itinerary> { >> let isCommutable = isComm; >> let isReMaterializable = 1; >> } >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...or example, if I want to increment it by 10. Can somebody show me what I'm doing wrong? Thanks. def ADS: F_J<0b100001,(outs),(ins i32imm:$amount),"ADS $amount",[(set SP, (add SP, i32imm:$amount))] > { bits<10> amount; let Inst{9-0} = amount; let isReMaterializable = 1; let mayLoad = 0; let mayStore = 0; let Defs = [SP]; let Uses = [SP]; } -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20181206/6ff8d7e0/attachment.html>

...// tablegen bug: should be I.OutOperandList, >>> I.InOperandList, >>> I.AsmString, >>> [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], >>> I.Itinerary> { >>> let isCommutable = isComm; >>> let isReMaterializable = 1; >>> } >>> _______________________________________________ >>> LLVM Developers mailing list >>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > >

...;: FRRR16<I.f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), // tablegen bug: should be I.OutOperandList, I.InOperandList, I.AsmString, [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], I.Itinerary > { let isCommutable = isComm; let isReMaterializable = 1; }

Hello, I'm getting a machine verifier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: let canFoldAsLoad = 1, isReMaterializable = 1, Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ : Inst<(outs DREGS:$dst), (ins memri:$src), "lddw\t$dst, $src", [(set DREGS:$dst, (load addr:$src))]>; This is just a load with displacement i...

...es in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src), "mov.w\t{$src, $dst}", [(set GR16:$dst, (load addr:$src))]>; } Please gvie me an explaination of the property IsReMaterialiable and the benefit if it is true wi...

...at I'm doing wrong? >> Thanks. >> >> def ADS: F_J<0b100001,(outs),(ins i32imm:$amount),"ADS $amount",[(set SP, (add SP, i32imm:$amount))] > { >> >> bits<10> amount; >> >> let Inst{9-0} = amount; >> let isReMaterializable = 1; >> let mayLoad = 0; >> let mayStore = 0; >> let Defs = [SP]; >> let Uses = [SP]; >> } > > What does the MCInst dump of this instruction look like? Have you looked > at YourTargetGenAsmWriter.inc to see which print methods are...

...> analysis. I don't think we want to remat general arithmetic quite yet. > At least that's not the intent of my change. I'll need some way to > identify "real" loads and I don't know of any other way other than > listing opcodes. Ideas? The target sets the isRematerializable bit on opcodes that are suitable for remat. That should be sufficient. You should also check the 'canFoldAsLoad' mechanism. /jakob

Hi Quentin, Sorry for the delay, I've been bogged down with other things today. On 14 July 2015 at 18:48, Quentin Colombet <qcolombet at apple.com> wrote: >> >> * A rematerializable interval once split is no longer rematerializable * >> >> The isRematerializable check in CalcSpillWeights.cpp uses the target >> instruction info to check that the machine instruction for the live >> interval definition is trivially rematerializable. In the case of >> interval A above, the definition is a load from the constant-pool. >> This is trivial...

...U16Regs:$rx), (ins CPU16Regs:$ry, CPU16Regs:$rz), > // tablegen bug: should be I.OutOperandList, I.InOperandList, > I.AsmString, > [(set CPU16Regs:$rx, (OpNode CPU16Regs:$ry, CPU16Regs:$rz))], > I.Itinerary > { > let isCommutable = isComm; > let isReMaterializable = 1; > } > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

....ferav at gmail.com> wrote: > Hello, > > I'm getting a machine verifier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: > > let canFoldAsLoad = 1, > isReMaterializable = 1, > Constraints = "@earlyclobber $dst" in > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > (ins memri:$src), > "lddw\t$dst, $src", > [(set DREGS:$dst, (load addr:$src))]>; > > This...

...gt; Hello, > > > > I'm getting a machine verifier error after introducing the earlyclobber > constraint to some instructions where the src and dest regs can't be the > same. The offending instruction pattern is this one: > > > > let canFoldAsLoad = 1, > > isReMaterializable = 1, > > Constraints = "@earlyclobber $dst" in > > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > > (ins memri:$src), > > "lddw\t$dst, $src", > > [(set DREGS:$dst, (load addr:$sr...

...es in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src), "mov.w\t{$src, $dst}", [(set GR16:$dst, (load addr:$src))]>; } Please gvie me an explaination of the property IsReMaterialiable and the benefit if it is true wi...

...n to be less target-dependent and to > make at least AliasAnalysis::pointsToConstantMemory queries. OK, I will have a look. I assume the reference to M_REMATERIALIZABLE in the comment for it should really be TID::Rematerializable? I also noticed that the documentation for TargetInstrDesc::isRematerializable() says "This flag is deprecated, please don't use it anymore" -- could you explain what replaces it? Stefanus -- Stefanus Du Toit <stefanus.dutoit at rapidmind.com> RapidMind Inc. phone: +1 519 885 5455 x116 -- fax: +1 519 885 1463

...gisters instead ? Looking at the ISel dump, for the above test-case: %0:tgpr, dead $cpsr = tMOVi8 10, 14, $noreg %1:tgpr, dead $cpsr = tMOVi8 20, 14, $noreg $r0 = COPY %0:tgpr $r1 = COPY %1:tgpr IIUC, there are a couple of reasons why this happens: (a) tMOVi8 pattern isn't marked with isRematerializable, isAsCheapAsMove, and isMoveImm. (b) After annotating the pattern with above flags, RegisterCoalescer::reMaterializeTrivialDef still bails out because the above assignment has 2 definitions, with only one live definition. To address this issue, I attached a hackish patch that (a) Marks tMOVi8 patt...

...> [RISCV][NFC] s/f32/f64 in double-arith.ll > > r352199 | asb | 2019-01-25 06:33:08 -0800 (Fri, 25 Jan 2019) | 8 lines > [RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombines > > r352008 | apazos | 2019-01-23 18:31:23 -0800 (Wed, 23 Jan 2019) | 9 lines > [RISCV] Set isReMaterializable for ORI, XORI > > On Wed, Jan 23, 2019 at 4:50 PM Hans Wennborg via llvm-dev > <llvm-dev at lists.llvm.org> wrote: > > > > Dear testers, > > > > 8.0.0-rc1 was just tagged (from the branch at r351980). > > > > It took a little longer than planned, b...

...bit isSimpleLoad = 0; // simple? bit mayLoad = 0; bit mayStore = 0; bit isTwoAddress = 0; // see question 1 bit isConvertibleToThreeAddress = 0; // see question 1 bit isCommutable = 0; // see rq1 below bit isTerminator = 0; // terminate what? A BB, A function, or the program bit isReMaterializable = 0; // ? bit isPredicable = 0; bit hasDelaySlot = 0; bit usesCustomDAGSchedInserter = 0; bit hasCtrlDep = 0; // ? bit isNotDuplicable = 0; // ? bit hasSideEffects = 0; bit mayHaveSideEffects = 0; // how is this different from has side effect? bit neverHasSideEffects = 1; Rq1: If...

...ge and what is the refined result after years of development. For example, everything went well with Cpu0RegisterInfo.td, with only a little struggle. But for Cpu0InstrInfo.td, questions start to come up: Why simm16 is inherited from Operand<i32>? What are PatLeaf and ComplexPattern? What is isReMaterializable? etc. Every line of description, every occurrence of new keyword or concept would confuse a beginner reader. They need to find enough information to follow this tutorial. This tutorial seems to tell that you have to write these 10 files, completely, without error, to continue to the next step. And...