llvm dev - Jul 2010 - [LLVMdev] How to specify patterns for instructions with accumulator in selection DAG?

Hi,

I am wondering how to specify the selection DAG patterns for instructions
that use accumulator.
For example multiply-accumulate instruction with one destination operand and
two source operands:
mac $dst, $src1, $src2 ;; $dst += $src1*$src2

Seems that it has a cycle in the pattern. So how do I specify it in the DAG?
There are a few instructions in the ARM backend like this one, but the
patterns are left blank.
-- 

Regards,

Dongrui
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On Jul 26, 2010, at 3:03 AM, Dongrui She wrote:
> Hi,
> 
> I am wondering how to specify the selection DAG patterns for instructions
that use accumulator.
> For example multiply-accumulate instruction with one destination operand
and two source operands:
> mac $dst, $src1, $src2 ;; $dst += $src1*$src2
> 
> Seems that it has a cycle in the pattern. So how do I specify it in the
DAG?
> There are a few instructions in the ARM backend like this one, but the
patterns are left blank.
Instructions where the output register must be one of the input registers are
called two-address instructions.

They are extremely common in x86, not so much in RISC architectures.

Two-address instructions look like normal three-address instructions in the
selection DAG except the have "Constraints" set. From
MSP430InstrInfo.td:

let Constraints = "$src = $dst" in {

def ADD8rr  : I8rr<0x0,
                   (outs GR8:$dst), (ins GR8:$src, GR8:$src2),
                   "add.b\t{$src2, $dst}",
                   [(set GR8:$dst, (add GR8:$src, GR8:$src2)),
                    (implicit SRW)]>;
def ADD16rr : I16rr<0x0,
                    (outs GR16:$dst), (ins GR16:$src, GR16:$src2),
                    "add.w\t{$src2, $dst}",
                    [(set GR16:$dst, (add GR16:$src, GR16:$src2)),
                     (implicit SRW)]>;
}

In your case, the MAC pattern would be:

let Constraints = "$acc = $dst" in
def MAC : ... (set $dst, (add $acc, (mul src1, src2)))