search for: add16rr

...t;, [(set GR16:$dst, (add GR16:$src1, (mul GR16:$src2, GR16:$src3)))]> } How can i tell the system X=A*B + C == X = B*A + C == X=C+A*B == X=C+B*A by property 'isCommutable'? Is it necessary to do that? *** Another question: Why set isCommutable = 1 in ADD16rr but NOT set in ADD16ri? let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "add.w\t{$src2, $dst}", [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),...

...1 in { def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src), "mov.w\t{$src, $dst}", [(set GR16:$dst, (load addr:$src))]>; } Please gvie me an explaination of the property IsReMaterialiable and the benefit if it is true with a simple sample 3 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "add.w\t{$src2, $dst}", [(set GR16:$dst, (add GR16:$src1, GR16:$src2)), (implicit SRW)]>; What informaton instuction selector will get by '(implicit SRW)'...

...ty 'isCommutable'? Is it necessary to do that? Most probably you will need to write a special hook to commute this instruction. However, everything depends on your target (e.g. if there is an output register tied to one of the input). > *** Another question: Why set isCommutable = 1 in ADD16rr but NOT set in > ADD16ri? Because all msp430 instructions are two-address, this means that output register is tied to first input. That's why you cannot swap operands for reg-imm operations. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg Sta...

...1 in { def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src), "mov.w\t{$src, $dst}", [(set GR16:$dst, (load addr:$src))]>; } Please gvie me an explaination of the property IsReMaterialiable and the benefit if it is true with a simple sample 3 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2), "add.w\t{$src2, $dst}", [(set GR16:$dst, (add GR16:$src1, GR16:$src2)), (implicit SRW)]>; What informaton instuction selector will get by '(implicit SRW)'...

...e an example to demonstrate what benifit it has if 'isCommuatble=1' in instruction selection, register allocation or other process? Regards 2009/12/7, Anton Korobeynikov <anton at korobeynikov.info>: > > Hello > > > *** Another question: Why set isCommutable = 1 in ADD16rr but NOT set in > > ADD16ri? > Because all msp430 instructions are two-address, this means that > output register is tied to first input. That's why you cannot swap > operands for reg-imm operations. > > -- > With best regards, Anton Korobeynikov > Faculty of Mathemati...

Hi, I am wondering how to specify the selection DAG patterns for instructions that use accumulator. For example multiply-accumulate instruction with one destination operand and two source operands: mac $dst, $src1, $src2 ;; $dst += $src1*$src2 Seems that it has a cycle in the pattern. So how do I specify it in the DAG? There are a few instructions in the ARM backend like this one, but the

Evan Cheng wrote: > On Apr 16, 2009, at 3:17 PM, Greg McGary wrote: > >> Is there some optimizer knob I'm not turning properly? In more complex >> cases, GCC does poorly with two-address operand choices and so bloats >> the code with unnecessary register moves. I have high hopes LLVM >> can do better, so this result for a simple case is bothersome. >>

Greetings, LLVM devs, For the past few weeks, I have been putting together a 6502 backend for LLVM. The 6502 and its derivatives, of course, have powered countless microcomputers, game consoles and arcade machines over the past 40 years. The backend is just an experimental hobby project right now. The code is available here: <https://github.com/beholdnec/llvm-m6502>. This branch introduces