search for: msp430instrinfo

...statement change to utils/TableGen/DAGISelMatcherGen.cpp -- something about variadic instructions that was probably OK for x86, but MSP430 doesn't have variadic instructions -- restored the correct behavior. Seems like r98938 either introduced a bug in DAGISelMatcherGen.cpp or exposed a bug in MSP430InstrInfo.td (or similar). That's Chris's commit; could he or someone else who's comfortable with LLVM internals (I'm not) help me root out the problem? I'm asking here because I don't know if this change broke other non-x86 architectures. -ben

Hello, I'm considering creating an LLVM backend for a 16 bit processor and modelling it around the (experimental) MSP430 back end. When reviewing MSP430InstrInfo.td I see def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; and can see in MSP430ISelLowering.cpp that ISD::GlobalAddress: ISD::BlockAddress: ISD::ExternalSymbol all get lowered to MSP430ISD::Wrapper(address space) plus the wrapped address node. What has me m...

...utils/TableGen/DAGISelMatcherGen.cpp -- something about variadic > instructions that was probably OK for x86, but MSP430 doesn't have > variadic instructions -- restored the correct behavior.  Seems like > r98938 either introduced a bug in DAGISelMatcherGen.cpp or exposed a > bug in MSP430InstrInfo.td (or similar).  That's Chris's commit; could > he or someone else who's comfortable with LLVM internals (I'm not) > help me root out the problem? Anton graciously helped me out of band. I'm attaching his patch (recomputed against ToT), which fixes a bug in MSP430InstrI...

On 25 Jul 2012, at 04:49, Paul Shortis wrote: > Hello, > > I'm considering creating an LLVM backend for a 16 bit processor and > modelling it around the (experimental) MSP430 back end. > > When reviewing MSP430InstrInfo.td I see > > def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; > > and can see in MSP430ISelLowering.cpp that > > ISD::GlobalAddress: > ISD::BlockAddress: > ISD::ExternalSymbol > > all get lowered to MSP430ISD::Wrapper(address spa...

Hello, I'm considering creating an LLVM backend for a 16 bit processor and modelling it around the (experimental) MSP430 back end. When reviewing MSP430InstrInfo.td I see def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; and can see in MSP430ISelLowering.cpp that ISD::GlobalAddress: ISD::BlockAddress: ISD::ExternalSymbol all get lowered to MSP430ISD::Wrapper(address base) plus the wrapped address node. What has me mys...

Hi, 1. This instruction is not selected automatically by the instruction selector. The instruction combine / select stages insert registercopies, and they are expanded later on by the copyRegToReg() function provided by the MSP430InstrInfo to this MOV16rr. 2. ReMaterializable means there is no need to find a way to preserve the value in a register : the instruction can be just be reissued whenever the value is needed. This remove some pressure on register alloc, and avoid unnecessary spilling. 3. It says that beside doing an add, i...

...t CPU) assembly as: add.w r13, r15 addc.w r12, r14 Using -print-before-all -print-after-all, I see that width splitting happens between last LLVM IR pass and first DAG pass dump. Using -view-* doesn't give insight either. Nor I was able to find any adhoc rules related to addc instruction in MSP430InstrInfo.td . So, it seems to be handled somewhere in target-independent code generator, can someone give a pointer to the code (and docs on this specific matter if any, because that's rather important machine-specific optimization topic IMHO, if you step aside from 32bit world). -- Best regards, P...

Hi everyone, I am puzzled by several instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects =

...18:21, Richard Osborne wrote: > On 25 Jul 2012, at 04:49, Paul Shortis wrote: > > >> Hello, >> >> I'm considering creating an LLVM backend for a 16 bit processor and >> modelling it around the (experimental) MSP430 back end. >> >> When reviewing MSP430InstrInfo.td I see >> >> def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; >> >> and can see in MSP430ISelLowering.cpp that >> >> ISD::GlobalAddress: >> ISD::BlockAddress: >> ISD::ExternalSymbol >> >> all get lower...

Hi, I am wondering how to specify the selection DAG patterns for instructions that use accumulator. For example multiply-accumulate instruction with one destination operand and two source operands: mac $dst, $src1, $src2 ;; $dst += $src1*$src2 Seems that it has a cycle in the pattern. So how do I specify it in the DAG? There are a few instructions in the ARM backend like this one, but the