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I have a question: In the pattern below from X86 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\tdst", [(set GR8:$dst, (add GR8:$src, 1))]>; Since we are emitting only "inc $dst", What makes sure that the $src and $dst are same register? - Sanjiv

sanjiv gupta wrote: > I have a question: > In the pattern below from X86 > > def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), > "inc{b}\tdst", > [(set GR8:$dst, (add GR8:$src, 1))]>; > > Since we are emitting only "inc $dst", > What makes sure that the $src and $dst are same register? > > - Sanjiv It's enclosed inside : let isTwoAddress = 1 i...

...l have other problems - not all instruction can select in InstructionSelection pass. My work place here: https://github.com/earl1k/llvm-z80 Example of some load instructions for Z80 CPU with opcode: Opcode Instruction node pattern 0x46 LD $dst,(HL) (set GR8:$dst, (load HL)) 0x0A LD A,(BC) (set A, (load BC)) 0x1A LD A,(DE) (set A, (load DE)) 0x3A LD A,($src) (set A, (load i16imm:$src)) Target Description file: ... let canFoldAsLoad = 1, isReMaterializable = 1 in { let Uses = [...

On Tue, 2008-09-23 at 13:33 +0100, Richard Osborne wrote: > sanjiv gupta wrote: > > I have a question: > > In the pattern below from X86 > > > > def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), > > "inc{b}\tdst", > > [(set GR8:$dst, (add GR8:$src, 1))]>; > > > > Since we are emitting only "inc $dst", > > What makes sure that the $src and $dst are same register? > > > > - Sanjiv > It's e...

I have some instructions that use a register as both an input and as the output. Is there a way to specify this constraint in the InstrInfo.td or will this have to be custom selected/lowered? Thanks -- Christopher Lamb christopher.lamb at gmail.com -------------- next part -------------- An HTML attachment was scrubbed... URL:

I see in the x86 InstInfo.td the following for the INC instructions: def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", [(set GR8:$dst, (add GR8:$src, 1))]>; Which seem to have the same restriction that I'm trying to implement, but I don't understand how this ensures that $src and $dst are the same register. -- Christopher Lamb christopher....

On Thu, 1 Mar 2007, Christopher Lamb wrote: > I see in the x86 InstInfo.td the following for the INC instructions: > > def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst", > [(set GR8:$dst, (add GR8:$src, 1))]>; > > Which seem to have the same restriction that I'm trying to implement, > but I don't understand how this ensures that $src and $dst are the > same register. The trick is...

...t; For an example we can look no further than the actual test which has been disabled after the fix (llvm/test/Codegen/X86/sink-hoist.ll, function zzz). > > BB#0: derived from LLVM BB %entry > %vreg0<def> = MOV8rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD1[FixedStack-2](align=4) GR8:%vreg0 > %vreg1<def> = AND8ri %vreg0, 127, %EFLAGS<imp-def,dead>; GR8:%vreg1,%vreg0 > %vreg2<def> = OR8ri %vreg0, -128, %EFLAGS<imp-def,dead>; GR8:%vreg2,%vreg0 > CMP8mi <fi#-1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[FixedStack-1](align=8...

...ll the time to filter out stack and frame pointers and other reserved registers. I was able to remove most of these custom allocation orders in the tree because the register allocators are now filtering out the reserved registers. A few instances remain. For example, x86 needs to remove AH-DH from GR8 in 64-bit mode because of the REX prefix encoding constraints. We don't want to reserve those four registers because they are still useful with some *_NOREX instructions. It looks like this: def GR8 : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH,...

Hi, I am wondering how to specify the selection DAG patterns for instructions that use accumulator. For example multiply-accumulate instruction with one destination operand and two source operands: mac $dst, $src1, $src2 ;; $dst += $src1*$src2 Seems that it has a cycle in the pattern. So how do I specify it in the DAG? There are a few instructions in the ARM backend like this one, but the

...is EFLAGS value. For an example we can look no further than the actual test which has been disabled after the fix (llvm/test/Codegen/X86/sink-hoist.ll, function zzz). BB#0: derived from LLVM BB %entry %vreg0<def> = MOV8rm <fi#-2>, 1, %noreg, 0, %noreg; mem:LD1[FixedStack-2](align=4) GR8:%vreg0 %vreg1<def> = AND8ri %vreg0, 127, %EFLAGS<imp-def,dead>; GR8:%vreg1,%vreg0 %vreg2<def> = OR8ri %vreg0, -128, %EFLAGS<imp-def,dead>; GR8:%vreg2,%vreg0 CMP8mi <fi#-1>, 1, %noreg, 0, %noreg, 0, %EFLAGS<imp-def>; mem:LD1[FixedStack-1](align=8) %vreg3<de...

...diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index e9a0431..f5b2064 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in { def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), "mov{b}\t{$src, $dst|$dst, $src}", [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; -def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), +def MOV16mr : I<0x89, MRMDestMem, (outs i16mem:$dst), (ins GR16:$src),...

...e; } SDNode *Select_ISD_ADDC_i8(const SDValue &N) { SDNode *Result = Emit_2(N, AVR::ADC, MVT::i8); return Result; } the related defines are: def ADC : RR<7, "adc $dst, $src2", addc>; class RR<bits<6> opcode, string asmstr, SDNode OpNode> : AVRInstr<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2), asmstr, [(set GR8:$dst, (OpNode GR8:$src1, GR8:$src2)), (implicit SREG)]> { let Inst{15-10} = opcode; } class AVRInstr<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction { field bits<16> Inst; let Namesp...

...t started, here are my first several questions and proposals. I hope that some of them make sense for you. 1. Why does X86 instruction set description provide different descriptions for the same instructions, which differ only in the size of operands? E.g. def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), "mov{b} {$src, $dst|$dst, $src}", [(set GR8:$dst, (load addr:$src))]>; def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), "mov{w} {$src, $dst|$dst, $src}", [(set GR16:$dst, (lo...

Dear, I am looking at the Instructions defined in the XXXXInstrInfo.td where I can see a def record defined like below def ADD8rr : I8rr<0x0, (outs GR8:$dst), (ins GR8:$src, GR8:$src2), "add.b\t{$src2, $dst}", [(set GR8:$dst, (*add *GR8:$src, GR8:$src2)), (implicit SRW)]>; Now here I would like the to replace the add(highlighted) by an arbitrary function say 'foo' (foo...

On Jun 3, 2011, at 2:59 AM, Galanov, Sergey wrote: > Hi, Bill and Jakob. > > I don't quite understand. I am talking about CMOV_GR* instructions which are conservatively marked as clobbering EFLAGS in X86InstrCompiler.td. Doesn't that mean there cannot be any use of EFLAGS in subsequent instructions before it is defined by some other instruction? > > I also don't

...ax states that it should be referenced as "%cl" while Intel says just "cl" but these references occur in X86InstInfo.td and this means that it is shared between Intel and ATT printing! For example, the shift rules: let Uses = [CL] in { def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src), "shl{b}\t{%cl, $dst|$dst, %CL}", [(set GR8:$dst, (shl GR8:$src, %CL))]>; def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src), "shl{w}\t{%cl, $dst|$dst, %CL}", [(se...

...stored in a pair of 8-bit > registers? One related question is how to make sure that the correct register pair is allocated to the16-bit quantity when using two 8-bit operations. In other words, how we can make sure that the 16-bit pointer is stored into [AH, AL] and not in [AH, BL] ? i.e. GR8 = [ AH, BH, AL, BL]; GR16 = [AX, BX] ; // AX, BX are subreg pairs of ah,al and bh, bl the DAG looks like Wrapper:i16 (GR16) = MoveToHi:i8 (GR8) , MoveToLo:i8 (GR8) Now how to make sure that if MoveToHi gets AH , then 1. MoveToLo should get AL, 2. the Wrapper should get A...

I am working on a project where we are integrating an existing pre-RA scheduler into LLVM and we are trying to match our peak register pressure values with the machine instruction schedulers values while using X86. I am finding some mismatches in test cases like the one attached. The registers "AH" and "AL" are live-out but not live-in and I don't see that they are defined

...estions and > proposals. I hope that some of them make sense for you. Ok. > 1. Why does X86 instruction set description provide different > descriptions for the same instructions, which differ only in the size > of operands? > E.g. > > def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), > "mov{b} {$src, $dst|$dst, $src}", > [(set GR8:$dst, (load addr:$src))]>; > def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), > "mov{w} {$src, $dst|$dst, $src}", >...