llvm dev - Dec 2009 - [LLVMdev] Questions of instruction target description of MSP430

Hi everyone,

I am puzzled by several instruction defines in MSP430.

1
def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
                     "mov.w\t{$src, $dst}",
                     [ ]>;
Because it's an empty  dag pattern[ ], by what does instuction selector
select intruction 'MOV16rr'?

 2
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
                "mov.w\t{$src, $dst}",
                [(set GR16:$dst, (load addr:$src))]>;
}
Please gvie me an explaination of the property IsReMaterialiable and the
benefit if it is true with a simple sample

 3
def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                     "add.w\t{$src2, $dst}",
                     [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
                      (implicit SRW)]>;
What informaton instuction selector will get by '(implicit SRW)'?
I can't understand 'implicit SRW' completely.


Regards
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Hi,

1. This instruction is not selected automatically by the instruction selector.
The instruction combine / select stages insert registercopies,  and they are
expanded later on by the copyRegToReg() function provided by the MSP430InstrInfo
to this MOV16rr.

2. ReMaterializable means there is no need to find a way to preserve the value
in a register : the instruction can be just be reissued whenever the value is
needed. This remove some pressure on register alloc, and avoid unnecessary
spilling.

3. It says that beside doing an add, it also affects (implicitly) the condition
codes. This enables to link this node to a following conditional  instruction,
using the condition codes. It is important that those 2 nodes stay stitched
together to ensure the condition codes are not clobbered by another instruction,
for example during instruction scheduling.

Best regards,
--
Arnaud de Grandmaison
________________________________________
From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] On Behalf
Of Heyu Zhu [zhu.heyu at gmail.com]
Sent: Friday, December 18, 2009 3:52 PM
To: llvmdev at cs.uiuc.edu
Subject: [LLVMdev] Questions of instruction target description of MSP430

Hi everyone,

I am puzzled by several instruction defines in MSP430.

1
def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
                     "mov.w\t{$src, $dst}",
                     [ ]>;
Because it's an empty  dag pattern[ ], by what does instuction selector
select intruction 'MOV16rr'?

 2
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
                "mov.w\t{$src, $dst}",
                [(set GR16:$dst, (load addr:$src))]>;
}
Please gvie me an explaination of the property IsReMaterialiable and the benefit
if it is true with a simple sample

 3
def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                     "add.w\t{$src2, $dst}",
                     [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
                      (implicit SRW)]>;
What informaton instuction selector will get by '(implicit SRW)'?
I can't understand 'implicit SRW' completely.


Regards

Hi Arnaud,

Thank you for your patient explanation.

Regards

2009/12/19 Arnaud Allard de Grandmaison <
Arnaud.AllardDeGrandMaison at dibcom.com>
> Hi,
>
> 1. This instruction is not selected automatically by the instruction
> selector. The instruction combine / select stages insert registercopies,
>  and they are expanded later on by the copyRegToReg() function provided by
> the MSP430InstrInfo to this MOV16rr.
>
> 2. ReMaterializable means there is no need to find a way to preserve the
> value in a register : the instruction can be just be reissued whenever the
> value is needed. This remove some pressure on register alloc, and avoid
> unnecessary spilling.
>
> 3. It says that beside doing an add, it also affects (implicitly) the
> condition codes. This enables to link this node to a following conditional
>  instruction, using the condition codes. It is important that those 2 nodes
> stay stitched together to ensure the condition codes are not clobbered by
> another instruction, for example during instruction scheduling.
>
> Best regards,
> --
> Arnaud de Grandmaison
> ________________________________________
> From: llvmdev-bounces at cs.uiuc.edu [llvmdev-bounces at cs.uiuc.edu] On
Behalf
> Of Heyu Zhu [zhu.heyu at gmail.com]
> Sent: Friday, December 18, 2009 3:52 PM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] Questions of instruction target description of MSP430
>
> Hi everyone,
>
> I am puzzled by several instruction defines in MSP430.
>
> 1
> def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src),
>                     "mov.w\t{$src, $dst}",
>                     [ ]>;
> Because it's an empty  dag pattern[ ], by what does instuction selector
> select intruction 'MOV16rr'?
>
>  2
> let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
> def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
>                "mov.w\t{$src, $dst}",
>                [(set GR16:$dst, (load addr:$src))]>;
> }
> Please gvie me an explaination of the property IsReMaterialiable and the
> benefit if it is true with a simple sample
>
>  3
> def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
>                     "add.w\t{$src2, $dst}",
>                     [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
>                      (implicit SRW)]>;
> What informaton instuction selector will get by '(implicit SRW)'?
> I can't understand 'implicit SRW' completely.
>
>
> Regards
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
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