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The only multiplication instruction on my target CPU is multiply-and-accumulate. The result goes into a special register that can destructively read at the end of a sequence of multiply-adds. The following sequence is required to so a simple multiply: acc r0 # clear accumulator, discarding its value (r0 reads as 0, and sinks writes) mac rSRC1, rSRC2 # multiply sources, store result in accumulator acc rDEST # fetch accumulator value to rDEST What's the best way to model simple MUL as this 3-insn sequence in the LLVM backend? Should the internal accumula...

...25, 2013 at 4:02 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk>wrote: > > On Mar 25, 2013, at 2:51 PM, Akira Hatanaka <ahatanak at gmail.com> wrote: > > > Yes, it sounds like it will solve the problem. > > > > Using the following example where live ranges of accumulators $vreg_acc0 > and $vreg_acc1 conflict, > > > > MULT $vreg_acc0, $vreg_gpr0, $vreg_gpr1 > > MULT $vreg_acc1, $vreg_gpr2, $vreg_gpr3 > > > > (consumer of $vreg_acc1) > > (consumer of $vreg_acc0) > > > > if the register can create new virtual register...

...The only multiplication instruction on my target CPU is > multiply-and-accumulate. The result goes into a special register that > can destructively read at the end of a sequence of multiply-adds. The > following sequence is required to so a simple multiply: > > acc r0 # clear accumulator, discarding its value (r0 reads as 0, > and sinks writes) > mac rSRC1, rSRC2 # multiply sources, store result in accumulator > acc rDEST # fetch accumulator value to rDEST > > What's the best way to model simple MUL as this 3-insn sequence in the > LLVM backend? >...

On Mar 26, 2013, at 10:29 AM, Akira Hatanaka <ahatanak at gmail.com> wrote: > The size of general purpose integer registers for mips32 is 32-bit and accumulators are 64-bit registers consisting of 32-bit hi/lo register pairs. So you will need two instructions to copy two 32-bit GPR registers to a 64-bit accumulator register. If spilling to multiple registers is unsupported, perhaps I can I define a new register class consisting of paired GPR registers and...

On Mar 25, 2013, at 2:51 PM, Akira Hatanaka <ahatanak at gmail.com> wrote: > Yes, it sounds like it will solve the problem. > > Using the following example where live ranges of accumulators $vreg_acc0 and $vreg_acc1 conflict, > > MULT $vreg_acc0, $vreg_gpr0, $vreg_gpr1 > MULT $vreg_acc1, $vreg_gpr2, $vreg_gpr3 > > (consumer of $vreg_acc1) > (consumer of $vreg_acc0) > > if the register can create new virtual registers $vreg_gpr4 and $vreg_gpr5, I think spill...

Hi to everyone, I am starting to work with a model that is not familiar to me. The model would be like that: y = . - a*max(Q(i) - Q(0), 0) + . where Q(i) is the accumulated effect of a variable at time i and Q(0) a threshold above it there is effect on y. The value of Q(i) could be estimated as: Q(i+1) = Q(i) + b*max(s(i) - s(0), 0) + c*min(s(i) - s(0), 0) + . Where s

In the precompute_partition_info_sums_ function, instead of selecting 64-bit accumulator when the signal bps is larger than 16, revert to the original approach based on partition size, but make room for few extra bits to not overflow with unusual signals where the average residual magnitude may be larger than bps. It slightly improves the performance with standard encoding levels and...

...extra stack slot might not be a big > problem, but still it is nice if we can avoid allocating a slot > unnecessarily. > > > > I probably won't need these pseudo instructions that are expanded > post-RA in the first place if I can tell the register allocators to spill > accumulator registers to general purpose integer registers instead of > directly to stack and disallow copying between accumulator registers. But I > guess that is a much more difficult problem to solve. Is that right? > > That depends. > > The register allocator can spill across register cla...

...a Subtarget of the Sparc target. The documentation for the processor is as follows: === To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made up by the 8 lsb bits from the %y register and the %asr18 register. The least significant 32 bits are also written to the destination register. SMAC works similarly but performs signed multiply and accumulate. The MAC instructions execute in one clock but have two clocks latency, meaning that o...

...faster on a 32 or 16 bit processor. If you >> would find the opposite to be true (ie that a 64 bit implementation is >> faster on, say, a 32 bit ARM CPU) then perhaps we should reconsider. >> > > Doesn't ARMv6 have a dual signed 16x16->32 multiply with a 64-bit > accumulator (SMLALD)? Even v5E should have a single 16x16->32 with a 64-bit > accumulator (SMLALBB). I would think a 64-bit version could be made pretty > fast on 32-bit ARM, without even resorting to SIMD. > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lis...

Hi, I post the question again. x<-rep(c(2,3,4),20) y<-sample(rep(c(0,1),30)) tr<-rep(c(1:5),6) data1<-data.frame(x,y,tr) data1<-data1[order(data1$tr),] > data1 x y tr 2 1 1 4 0 1 3 1 1 2 1 1 4 1 1 3 1 1 2 0 1 4 0 1 3 0 1 2 0 1 4 0 1 3 1 1 3 0 2 2 0 2 >table(data1) tr = 1 y x 0 1 2 2 2 3 1 3 4 3 1 tr = 2 y x 0 1 2 2 2 3 2 2 4 1 3

Hello! I'm a PhD student working with coral reef fish diversity in Mexico. I want to do species accumulation curves but I have differential sampling effort for each "sample". Do you know or have developed an R script that consider the differential effort of each sample? PRIMER and other programs use each pack of species as a replica without the possibility of telling the program that

Hi, I am wondering how to specify the selection DAG patterns for instructions that use accumulator. For example multiply-accumulate instruction with one destination operand and two source operands: mac $dst, $src1, $src2 ;; $dst += $src1*$src2 Seems that it has a cycle in the pattern. So how do I specify it in the DAG? There are a few instructions in the ARM backend like this one, but the patte...

...a Subtarget of the Sparc target. The documentation for the processor is as follows: === To accelerate DSP algorithms, two multiply&accumulate instructions are implemented: UMAC and SMAC. The UMAC performs an unsigned 16-bit multiply, producing a 32-bit result, and adds the result to a 40-bit accumulator made up by the 8 lsb bits from the %y register and the %asr18 register. The least significant 32 bits are also written to the destination register. SMAC works similarly but performs signed multiply and accumulate. The MAC instructions execute in one clock but have two clocks latency, meaning that o...

On Fri, Jun 20, 2014 at 01:21:03PM +0400, lvqcl wrote: > Miroslav Lichvar ?????: > > > +/* > > + * This is used to avoid overflow with unusual signals in 32-bit > > + * accumulator in the *precompute_partition_info_sums_* functions. > > + */ > > +#define FLAC__MAX_EXTRA_RESIDUAL_BPS 4 > > > + /* WATCHOUT: "+ bps + FLAC__MAX_EXTRA_RESIDUAL_BPS" is the maximum > > + * assumed size of the average residual magnitude */ > > + if(FLAC...

Hi All, Asterisk 1.4.12 CentOS 5 My ISP account includes nearly 500 minutes of VOIP calls per month but the service is expensive for unbundled minutes. So I'm trying to find a way to keep an accumulated total of calls made through that trunk so that I can automatically switch to a lower-cost provider when my bundled minutes are used. The plan is to store the accumulated time in AstDB and

.... > > > > https://git.xiph.org/?p=flac.git;a=commit;h=6f7ec60c7e7f05f5ab0b1cf6b7b0945e44afcd4b > > I don't like this fix. It will probably hurt performance with 16-bit > data and it won't fix the problem in the assembly code. > > I think the check if 32-bit accumulator is enough should be improved > instead if possible. Miroslav, I have committed an improvement on the above fix. https://git.xiph.org/?p=flac.git;a=commit;h=f34f31dac0032887887b5bbcb0944de055b757d0 that reverts to the use of a FLAC_uint32 accumulator for files of less than 24 bits per sam...

...:15, Brian Willoughby wrote: > What you need to do is write a bitStream function. It should only > read each byte from the stream once and completely deal with all 8 > bits before reading the next byte. You should never look ahead > beyond the current byte. Instead, you need an accumulator to > collect the incoming bits. Each time you read a byte, add 8 to > your bit count, and shift any existing bits in your accumulator > around to make room for the new bits. When pulling values out of > the accumulator, you do that based upon the number of bits > requeste...

Miroslav Lichvar wrote: > In the precompute_partition_info_sums_ function, instead of selecting > 64-bit accumulator when the signal bps is larger than 16, revert to the > original approach based on partition size, but make room for few extra > bits to not overflow with unusual signals where the average residual > magnitude may be larger than bps. > > It slightly improves the performance with stan...

...day, March 26, 2013 12:40:44 PM > Subject: Re: [LLVMdev] [PATCH] RegScavenger::scavengeRegister > > > On Mar 26, 2013, at 10:29 AM, Akira Hatanaka <ahatanak at gmail.com> > wrote: > > > The size of general purpose integer registers for mips32 is 32-bit > > and accumulators are 64-bit registers consisting of 32-bit hi/lo > > register pairs. So you will need two instructions to copy two > > 32-bit GPR registers to a 64-bit accumulator register. If spilling > > to multiple registers is unsupported, perhaps I can I define a new > > register class...