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Hi everyone, I am puzzled by several instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {...

In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register: def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>; def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; The SP can not be used in general purpose arithmetic instructions, therefore I defined the following classes in MyTargetInstrInfo.td: c...

Hi everyone, I practice writing target description file with MSP430 reference. I add a multiply-and-add instruction as below: let isTwoAddress=1 in { def MULADD:Pseudo<(out GR16:$dst), (ins GR16:$src1, GR16:$src2, GR16:$src3), "muladd\t{$dst, $src2, $src3}", [(set GR16:$dst, (add GR16:$src1, (mul GR16:$src2, GR16:$src3)))]> } How can i tell the system X=A*B + C == X = B*A + C == X=C+A*B == X=C...

....uiuc.edu] On Behalf Of Heyu Zhu [zhu.heyu at gmail.com] Sent: Friday, December 18, 2009 3:52 PM To: llvmdev at cs.uiuc.edu Subject: [LLVMdev] Questions of instruction target description of MSP430 Hi everyone, I am puzzled by several instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {...

...P+8] fi#-1: size=2, align=8, fixed, at location [SP+4] Function Live Outs: %AX BB#0: derived from LLVM BB %entry %reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390 %reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390 %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391 %reg16384<def> = COPY %reg16391:sub_16bit<kill>; GR16:%reg16384 GR32:%reg16391 Successors according to CFG: BB#1 ... 2: BB#0: derived...

...11:31 AM > To: via llvm-dev <llvm-dev at lists.llvm.org> > Subject: [EXT] [llvm-dev] Instruction is selected, but it shouldn't (?) > > In MyTargetRegisterInfo.td file, I defined separated register classes for general purpose registers and for the SP register: > > def GR16 : RegisterClass<"CPU74", [i16], 16, (add R0, R1, R2, R3, R4, R5, R6, R7)>; > def SSP : RegisterClass<"CPU74", [i16], 16, (add SP)>; > > The SP can not be used in general purpose arithmetic instructions, therefore I defined the following classes in MyTarget...

...let SchedRW = [WriteStore] in { def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), "mov{b}\t{$src, $dst|$dst, $src}", [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; -def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), +def MOV16mr : I<0x89, MRMDestMem, (outs i16mem:$dst), (ins GR16:$src), "mov{w}\t{$src, $dst|$dst, $src}", [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), ---...

Hi, I am wondering how to specify the selection DAG patterns for instructions that use accumulator. For example multiply-accumulate instruction with one destination operand and two source operands: mac $dst, $src1, $src2 ;; $dst += $src1*$src2 Seems that it has a cycle in the pattern. So how do I specify it in the DAG? There are a few instructions in the ARM backend like this one, but the

...on selection, the pseudo AMX instruction is > generated. The name of pseudo instructions have ‘P’ prefix. Now all > the AMX pseudo instruction take vtile as register class. Let’s assume > %13 is constant 3, %10 is constant 4 and %14 is variable. > > /  %1:vtile = *P*TILELOADDV %13:gr16, %10:gr16, %17:gr64, 1, > %18:gr64_nosp, 0, $noreg/ > > /  %2:vtile = *P*TILELOADDV %10:gr16, %14:gr16, %17:gr64, 1, > %18:gr64_nosp, 0, $noreg/ > > /  %3:vtile = *P*TILELOADDV %13:gr16, %14:gr16, %17:gr64, 1, > %18:gr64_nosp, 0, $noreg/ > > /%21:vtile = *P*TDPBSSDV %1...

Evan Cheng wrote: > On Apr 16, 2009, at 3:17 PM, Greg McGary wrote: > >> Is there some optimizer knob I'm not turning properly? In more complex >> cases, GCC does poorly with two-address operand choices and so bloats >> the code with unnecessary register moves. I have high hopes LLVM >> can do better, so this result for a simple case is bothersome. >>

...for the same instructions, which differ only in the size of operands? E.g. def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), "mov{b} {$src, $dst|$dst, $src}", [(set GR8:$dst, (load addr:$src))]>; def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), "mov{w} {$src, $dst|$dst, $src}", [(set GR16:$dst, (load addr:$src))]>, OpSize; def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), "mov{l} {$src, $dst|$dst, $src}", [(set GR32:$...

...%EX<imp-def>, %SP<imp-use> CALLi <ga:@clock_get_ticks>, <regmask>, %SP<imp-use>, %SP<imp-def>, %A<imp-def>, ... ADJCALLSTACKUP 0, 0, %SP<imp-def>, %EX<imp-def>, %SP<imp-use> %vreg57<def> = COPY %A<kill>; GR16:%vreg57 %vreg58<def> = SUB16rr %vreg57, %vreg18<kill>, %EX<imp-def>; GR16:%vreg58,%vreg57 GEXR16:%vreg18 %vreg59<def> = ADD16rm %vreg58<kill>, <fi#1>, 16, %EX<imp-def>; mem:LD1[%sunkaddr21](align=8)(tbaa=!"int") GR16:%vreg59,%vreg5...

...ATT printing! For example, the shift rules: let Uses = [CL] in { def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src), "shl{b}\t{%cl, $dst|$dst, %CL}", [(set GR8:$dst, (shl GR8:$src, %CL))]>; def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src), "shl{w}\t{%cl, $dst|$dst, %CL}", [(set GR16:$dst, (shl GR16:$src, %CL))]>, OpSize; def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src), "shl{l}\t{%cl, $dst|$dst, %CL}",...

...the pseudo AMX instruction is > generated. The name of pseudo instructions have ‘P’ prefix. Now > all the AMX pseudo instruction take vtile as register class. Let’s > assume %13 is constant 3, %10 is constant 4 and %14 is variable. > > /  %1:vtile = *P*TILELOADDV %13:gr16, %10:gr16, %17:gr64, 1, > %18:gr64_nosp, 0, $noreg/ > > /  %2:vtile = *P*TILELOADDV %10:gr16, %14:gr16, %17:gr64, 1, > %18:gr64_nosp, 0, $noreg/ > > /  %3:vtile = *P*TILELOADDV %13:gr16, %14:gr16, %17:gr64, 1, > %18:gr64_nosp, 0, $noreg/ > > /%21:v...

...h differ only in the size > of operands? > E.g. > > def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src), > "mov{b} {$src, $dst|$dst, $src}", > [(set GR8:$dst, (load addr:$src))]>; > def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src), > "mov{w} {$src, $dst|$dst, $src}", > [(set GR16:$dst, (load addr:$src))]>, OpSize; > def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src), > "mov{l} {$src, $dst|$dst, $src}", >...

...gt; = COPY %reg16390. Furthermore, how should I handle this case. > BB#0: derived from LLVM BB %entry > %reg16390<def> = MOVZX32rm16 <fi#-2>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-2] GR32:%reg16390 > %reg16385<def> = COPY %reg16390:sub_16bit<kill>; GR16:%reg16385 GR32:%reg16390 > %reg16391<def> = MOVZX32rm16 <fi#-1>, 1, %reg0, 0, %reg0; mem:LD2[FixedStack-1] GR32:%reg16391 > %reg16384<def> = COPY %reg16391:sub_16bit<kill>; GR16:%reg16384 GR32:%reg16391 > Successors according to CFG: BB#1 Machin...

...e","f"]>; } let SubRegIndices = [sub_hi_word, sub_lo_word], CoveredBySubRegs = 1 in { def AQ : MC6809RegWithSubregs<0, "q", [AD,AW], ["d","w"]>; } def GR8 : RegisterClass<"MC6809", [i8], 8, (add AA, AB, CC, DP, AE, AF)>; def GR16 : RegisterClass<"MC6809", [i16], 8, (add AD, IX, IY, SU, SS, PC, AW, AV, A0)>; def GR32 : RegisterClass<"MC6809", [i32], 8, (add AQ)>; def IX16 : RegisterClass<"MC6809", [i16], 8, (add IX, IY, SU, SS)>; def WREG : RegisterClass<"MC6809&quot...

...After instruction selection, the pseudo AMX instruction is generated. The name of pseudo instructions have 'P' prefix. Now all the AMX pseudo instruction take vtile as register class. Let's assume %13 is constant 3, %10 is constant 4 and %14 is variable. %1:vtile = PTILELOADDV %13:gr16, %10:gr16, %17:gr64, 1, %18:gr64_nosp, 0, $noreg %2:vtile = PTILELOADDV %10:gr16, %14:gr16, %17:gr64, 1, %18:gr64_nosp, 0, $noreg %3:vtile = PTILELOADDV %13:gr16, %14:gr16, %17:gr64, 1, %18:gr64_nosp, 0, $noreg %21:vtile = PTDPBSSDV %13:gr16, %10:gr16, %14:gr16, %3:vtile(tied-def 0), %1:vtile,...

I am new to the LLVM backends, I am wondering how instruction selection is done in LLVM backends, I looked at the .td files in Target/X86, they all seem to be small and do not deal with common X86 instructions, i.e. mov, push, pop, etc. Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL:

...> registers? One related question is how to make sure that the correct register pair is allocated to the16-bit quantity when using two 8-bit operations. In other words, how we can make sure that the 16-bit pointer is stored into [AH, AL] and not in [AH, BL] ? i.e. GR8 = [ AH, BH, AL, BL]; GR16 = [AX, BX] ; // AX, BX are subreg pairs of ah,al and bh, bl the DAG looks like Wrapper:i16 (GR16) = MoveToHi:i8 (GR8) , MoveToLo:i8 (GR8) Now how to make sure that if MoveToHi gets AH , then 1. MoveToLo should get AL, 2. the Wrapper should get AX - Sanjiv On Sep 19,...