Displaying 12 results from an estimated 12 matches for "mov16rm".
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mov16mr
2015 Dec 04
2
analyzePhysReg question
...n I expected for x86.
The call to this is coming from this code in llvm::MachineBasicBlock::computeRegisterLiveness
1163 MachineOperandIteratorBase::PhysRegInfo Analysis =
1164 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
The instruction I being analyzed is:
%BX<def> = MOV16rm %EDI, 2, %ECX, 0, %noreg; mem:LD2[%arrayidx98](tbaa=!18)
and the Reg being passed in is 21, which is EBX. The result I get back for is:
Analysis: {Clobbers = true, Defines = true, Reads = false, ReadsOverlap = false,
DefinesDead = false, Kills = false}
It seems based on the comment in the def...
2009 Dec 18
2
[LLVMdev] Questions of instruction target description of MSP430
...), (ins GR16:$src),
"mov.w\t{$src, $dst}",
[ ]>;
Because it's an empty dag pattern[ ], by what does instuction selector
select intruction 'MOV16rr'?
2
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
"mov.w\t{$src, $dst}",
[(set GR16:$dst, (load addr:$src))]>;
}
Please gvie me an explaination of the property IsReMaterialiable and the
benefit if it is true with a simple sample
3
def ADD16rr : Pseudo&l...
2010 Jun 03
2
[LLVMdev] Unused argument registers can not be reused ?
...ugh +[0,40:0)
livein register: R14B dead +[0,3:0)
livein register: R13W live through +[0,40:0)
livein register: R13B dead +[0,3:0)
livein register: R12W live through +[0,40:0)
livein register: R12B dead +[0,3:0)
4 %reg1028<def> = MOV16rm %reg0, <ga:@b>; mem:LD2[@b]
register: %reg1028 +[6,14:0)
12 %reg1029<def> = MOV16rr %reg1028<kill>
register: %reg1029 +[14,30:0)
20 %reg1029<def> = ADD16rm %reg1029, %reg0, <ga:@a>, %SRW<imp-def>; mem:LD2[@a]
register: %r...
2010 Jun 03
0
[LLVMdev] FW: Unused argument registers can not be reused ?
...6, %R12W in reg%1027
BB#0: derived from LLVM BB %entry
Live Ins: %R15W %R14W %R13W %R12W
%reg1027<def> = MOV16rr %R12W
%reg1026<def> = MOV16rr %R13W
%reg1025<def> = MOV16rr %R14W
%reg1024<def> = MOV16rr %R15W
%reg1028<def> = MOV16rm %reg0, <ga:@b>; mem:LD2[@b]
%reg1029<def> = ADD16rm %reg1028, %reg0, <ga:@a>, %SRW<imp-def,dead>; mem:LD2[@a]
SUB16mr %reg0, <ga:@r>, %reg1029, %SRW<imp-def,dead>; mem:ST2[@r] LD2[@r]
RET
# End machine code for function test.
# Machine c...
2015 Dec 04
2
analyzePhysReg question
...ng from this code in
>llvm::MachineBasicBlock::computeRegisterLiveness
>> 1163 MachineOperandIteratorBase::PhysRegInfo Analysis =
>> 1164 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
>>
>> The instruction I being analyzed is:
>> %BX<def> = MOV16rm %EDI, 2, %ECX, 0, %noreg;
>mem:LD2[%arrayidx98](tbaa=!18)
>>
>> and the Reg being passed in is 21, which is EBX. The result I get back for
>is:
>>
>> Analysis: {Clobbers = true, Defines = true, Reads = false, ReadsOverlap =
>false,
>> DefinesDead = false, Ki...
2009 Dec 19
0
[LLVMdev] Questions of instruction target description of MSP430
...), (ins GR16:$src),
"mov.w\t{$src, $dst}",
[ ]>;
Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'?
2
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
"mov.w\t{$src, $dst}",
[(set GR16:$dst, (load addr:$src))]>;
}
Please gvie me an explaination of the property IsReMaterialiable and the benefit if it is true with a simple sample
3
def ADD16rr : Pseudo&l...
2015 Dec 04
2
analyzePhysReg question
...sicBlock::computeRegisterLiveness
>>>> 1163 MachineOperandIteratorBase::PhysRegInfo Analysis =
>>>> 1164 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
>>>>
>>>> The instruction I being analyzed is:
>>>> %BX<def> = MOV16rm %EDI, 2, %ECX, 0, %noreg;
>>> mem:LD2[%arrayidx98](tbaa=!18)
>>>>
>>>> and the Reg being passed in is 21, which is EBX. The result I get back for
>>> is:
>>>>
>>>> Analysis: {Clobbers = true, Defines = true, Reads = false, ReadsOv...
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
...iption provide different
descriptions for the same instructions, which differ only in the size
of operands?
E.g.
def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
"mov{b} {$src, $dst|$dst, $src}",
[(set GR8:$dst, (load addr:$src))]>;
def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src),
"mov{w} {$src, $dst|$dst, $src}",
[(set GR16:$dst, (load addr:$src))]>, OpSize;
def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src),
"mov{l} {$src, $dst|$dst, $src}&q...
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
...tions for the same instructions, which differ only in the size
> of operands?
> E.g.
>
> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
> "mov{b} {$src, $dst|$dst, $src}",
> [(set GR8:$dst, (load addr:$src))]>;
> def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src),
> "mov{w} {$src, $dst|$dst, $src}",
> [(set GR16:$dst, (load addr:$src))]>, OpSize;
> def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src),
> "mov{l} {$src, $...
2012 Jul 04
2
[LLVMdev] Assertion in PHIElimination.cpp
...<imp-def>; mem:LD1[%sunkaddr21](align=8)(tbaa=!"int") GR16:%vreg59,%vreg58
MOV16mr <fi#1>, 16, %vreg59; mem:ST1[%sunkaddr21](align=8)(tbaa=!"int") GR16:%vreg59
%vreg20<def> = COPY %vreg59; GEXR16:%vreg20 GR16:%vreg59
%vreg21<def> = MOV16rm <fi#1>, 15; mem:LD1[%sunkaddr24](tbaa=!"int") GEXR16:%vreg21
%vreg81<def> = COPY %vreg21; GEXR16:%vreg81,%vreg21
BR_CCrr 2, %vreg59, %vreg21, <BB#10>; GR16:%vreg59 GEXR16:%vreg21
BR_CCrr 7, %vreg59<kill>, %vreg21, <BB#10>; GR16:%vreg59...
2015 Dec 04
2
analyzePhysReg question
...gt;>
>> llvm::MachineBasicBlock::computeRegisterLiveness
>>
>> 1163 MachineOperandIteratorBase::PhysRegInfo Analysis =
>> 1164 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
>>
>> The instruction I being analyzed is:
>> %BX<def> = MOV16rm %EDI, 2, %ECX, 0, %noreg;
>>
>> mem:LD2[%arrayidx98](tbaa=!18)
>>
>>
>> and the Reg being passed in is 21, which is EBX. The result I get back for
>>
>> is:
>>
>>
>> Analysis: {Clobbers = true, Defines = true, Reads = false, ReadsOverlap...
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
...ons, which differ only in the
size
>> of operands?
>> E.g.
>>
>> def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
>> "mov{b} {$src, $dst|$dst, $src}",
>> [(set GR8:$dst, (load addr:$src))]>;
>> def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src),
>> "mov{w} {$src, $dst|$dst, $src}",
>> [(set GR16:$dst, (load addr:$src))]>, OpSize;
>> def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src),
>> "...