search for: canfoldasload

...; As far as a long-term solution, would it be > > better to update TableGen with this logic instead of putting this in > > ISel? > > -Hal > > > Also, we should probably include hasUnmodeledSideEffects along > > with mayLoad and mayStore. I also had to include II.canFoldAsLoad to make this work for me. As is the case with other "simple" loads in the PowerPC backend, canFoldAsLoad is set but mayLoad is not (is this wrong)? Thanks again, Hal > > > > -Hal > > > > > > > > Tim. > > > > > > > > &g...

> I also had to include II.canFoldAsLoad to make this work for me. As is > the case with other "simple" loads in the PowerPC backend, > canFoldAsLoad is set but mayLoad is not (is this wrong)? Hmm. So far we've got: mayLoad, mayStore, canFoldAsLoad and hasUnmodeledSideEffects as candidates. Looking at Target.td, I se...

On Sun, 24 Jun 2012 10:18:00 +0100 Tim Northover <t.p.northover at gmail.com> wrote: > > I also had to include II.canFoldAsLoad to make this work for me. As > > is the case with other "simple" loads in the PowerPC backend, > > canFoldAsLoad is set but mayLoad is not (is this wrong)? > > Hmm. So far we've got: mayLoad, mayStore, canFoldAsLoad and > hasUnmodeledSideEffects as candidates. &g...

Hello, I'm getting a machine verifier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: let canFoldAsLoad = 1, isReMaterializable = 1, Constraints = "@earlyclobber $dst" in def LDDWRdPtrQ : Inst<(outs DREGS:$dst), (ins memri:$src), "lddw\t$dst, $src", [(set DREGS:$dst, (load addr:$src))]>; This is just a...

...l instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src), "mov.w\t{$src, $dst}", [(set GR16:$dst, (load addr:$src))]>; } Please gvie me an explaination of the property IsReMaterialiable and the...

...of my change. I'll need some way to > identify "real" loads and I don't know of any other way other than > listing opcodes. Ideas? The target sets the isRematerializable bit on opcodes that are suitable for remat. That should be sufficient. You should also check the 'canFoldAsLoad' mechanism. /jakob

..., Borja Ferrer <borja.ferav at gmail.com> wrote: > Hello, > > I'm getting a machine verifier error after introducing the earlyclobber constraint to some instructions where the src and dest regs can't be the same. The offending instruction pattern is this one: > > let canFoldAsLoad = 1, > isReMaterializable = 1, > Constraints = "@earlyclobber $dst" in > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > (ins memri:$src), > "lddw\t$dst, $src", > [(set DREGS:$dst, (load addr...

On Sat, 23 Jun 2012 21:18:37 -0500 Hal Finkel <hfinkel at anl.gov> wrote: > On Sat, 23 Jun 2012 22:28:55 +0100 > Tim Northover <t.p.northover at gmail.com> wrote: > > > On Sat, Jun 23, 2012 at 04:10:51PM -0500, Hal Finkel wrote: > > > Working on a target I added this pattern: > > > > > > def : Pat<(v4i64 (load xoaddr:$src)), > >

...il.com> wrote: > > > Hello, > > > > I'm getting a machine verifier error after introducing the earlyclobber > constraint to some instructions where the src and dest regs can't be the > same. The offending instruction pattern is this one: > > > > let canFoldAsLoad = 1, > > isReMaterializable = 1, > > Constraints = "@earlyclobber $dst" in > > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), > > (ins memri:$src), > > "lddw\t$dst, $src", > >...

...l instruction defines in MSP430. 1 def MOV16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src), "mov.w\t{$src, $dst}", [ ]>; Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'? 2 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in { def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src), "mov.w\t{$src, $dst}", [(set GR16:$dst, (load addr:$src))]>; } Please gvie me an explaination of the property IsReMaterialiable and the...

On Sat, 23 Jun 2012 22:28:55 +0100 Tim Northover <t.p.northover at gmail.com> wrote: > On Sat, Jun 23, 2012 at 04:10:51PM -0500, Hal Finkel wrote: > > Working on a target I added this pattern: > > > > def : Pat<(v4i64 (load xoaddr:$src)), > > (QVFCTIDb (QVLFDXb xoaddr:$src))>; > > > > I'd like to fix this so that it works

dag at cray.com (David A. Greene) writes: >>> The change requires that live interval analysis be able to determine >>> whether and instruction is a load and whether an instruction writes to >>> memory. >> >> Just use MI->mayLoad(), MI->mayStore(). > > Does this also account for arithmetic instructions with memops? These > interfaces

...gt; > Hello, >> > >> > I'm getting a machine verifier error after introducing the earlyclobber >> constraint to some instructions where the src and dest regs can't be the >> same. The offending instruction pattern is this one: >> > >> > let canFoldAsLoad = 1, >> > isReMaterializable = 1, >> > Constraints = "@earlyclobber $dst" in >> > def LDDWRdPtrQ : Inst<(outs DREGS:$dst), >> > (ins memri:$src), >> > "lddw\t$dst, $src", >> &gt...

Jakob Stoklund Olesen <stoklund at 2pi.dk> writes: > That's great, but I really wish you would discuss the design of these > things publicly, and not develop features on long-running secret > branches. If you secretly start out in the wrong direction, you could > be wasting a lot of your time. I don't have a choice. I have to get patches approved after I already have

...node pattern 0x46 LD $dst,(HL) (set GR8:$dst, (load HL)) 0x0A LD A,(BC) (set A, (load BC)) 0x1A LD A,(DE) (set A, (load DE)) 0x3A LD A,($src) (set A, (load i16imm:$src)) Target Description file: ... let canFoldAsLoad = 1, isReMaterializable = 1 in { let Uses = [HL] in def LD8rm : IRy<0x46, (outs GR8:$dst), (ins), "ld\t{$dst, (hl)}", [(set GR8:$dst, (load HL))]>; let Defs = [A], Uses = [BC] in def LD8AmBC : I<0x0A, (outs), (ins), "ld\t{a, (bc)}", [(set A, (load...

...^ | Note this one inconsistent bit One way to solve this solution would be to to describe them in InstrInfo.td as seperate instructions. Note that R27R26 is a pointer register defined in AVRRegisterInfo.td, and 'X' is an alias for this. let Uses = [R27R26], canFoldAsLoad = 1, isReMaterializable = 1 in def LDRdX : FSTLDPtrReg<0b0, (outs GPR8:$reg), (ins), "ld\t$reg, X", [(set GPR8:$reg, (load R27R26))]>; def LDRdY : FSTLDPtrReg<0b0, // ......