Displaying 6 results from an estimated 6 matches for "memsrc".
2009 Dec 18
2
[LLVMdev] Questions of instruction target description of MSP430
...uot;mov.w\t{$src, $dst}",
[ ]>;
Because it's an empty dag pattern[ ], by what does instuction selector
select intruction 'MOV16rr'?
2
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
"mov.w\t{$src, $dst}",
[(set GR16:$dst, (load addr:$src))]>;
}
Please gvie me an explaination of the property IsReMaterialiable and the
benefit if it is true with a simple sample
3
def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:...
2018 Feb 25
0
CodeEmitterGen generates wrong code for getBinaryCodeForInstr
Hi, It seems like CodeEmitterGen gets confused when we use named
suboperands.
sample code:
def memsrc : Operand<i16> {
let PrintMethod = "printSrcMemOperand";
let MIOperandInfo = (ops GR16:$ra, i16imm:$imm_i16);
let ParserMatchClass = memAsmOperand;
}
def LOAD16m : Inst32rri<0x0, (outs GR16:$rb), (ins memsrc:$src2),
"ldi16 {$rb, $src2}",...
2009 Dec 19
0
[LLVMdev] Questions of instruction target description of MSP430
...uot;mov.w\t{$src, $dst}",
[ ]>;
Because it's an empty dag pattern[ ], by what does instuction selector select intruction 'MOV16rr'?
2
let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
def MOV16rm : Pseudo<(outs GR16:$dst), (ins memsrc:$src),
"mov.w\t{$src, $dst}",
[(set GR16:$dst, (load addr:$src))]>;
}
Please gvie me an explaination of the property IsReMaterialiable and the benefit if it is true with a simple sample
3
def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:...
2013 Mar 20
2
[LLVMdev] Strange spill behaviour
....L\t{$dst,$src1 + $src2}",[(set GR32:$dst, (add
GR32:$src1, imm:$src2))]>;
def SUB32rrr : M819Inst<(outs GR32:$dst),(ins GR32:$src1,
GR32:$src2),"SUB.L\t{$dst,$src1 - $src2}",[(set GR32:$dst, (sub GR32:$src1,
GR32:$src2))]>;
def MOV32rm : M819Inst<(outs GR32:$dst), (ins memsrc:$src),"MOV.L\t{$dst,
[$src]}",[(set GR32:$dst,(load addr:$src))]>;
def MOV32mr : M819Inst<(outs), (ins memdst:$dst,
GR32:$src),"MOV.L\t{[$dst], $src}",[(store GR32:$src, addr:$dst)]>;
Am I misunderstanding something here?
Lee
-------------- next part -----------...
2012 Sep 26
0
[LLVMdev] Folding nodes with more than one use during ISel
...lised with the single CPU12 instruction which uses the indirect indexed addressing mode:
com [6,y]
I've defined a multiclass for this type of instruction in my InstrInfo.td and the relevant entry for this addressing mode is:
def IdxI16 : IdxPB2Inst<opcode, AddrModeIdxI16, (outs), (ins memsrc:$mem),
!strconcat (str, "\t[$mem]\t; IdxI16"),
[(store (OpNode (loadi8 (loadi16 addrIAny:$mem))),
(loadi16 addrIAny:$mem))>;
where loadi8 and loadi16 are PatFrags that match an i8 and i16 load res...
2016 Jun 22
2
LLVM Backend Issues
Thanks Anton and Krzysztof!
Here is the dump using the -debug flag. At this point I am not making much
sense of this, would it be too much to ask if one of you could walk me
through one of these lines?
One thing that I didn't point out is that I never defined any separate
floating point registers, not sure if this will pose any issue?
Thanks again for your time!
Jeff
jeff at