The thumb2 instructions include unsigned and signed divide. Attached are a patch and test routine. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: div.diff URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091201/675cf4c5/attachment.ksh> -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: div.ll URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091201/675cf4c5/attachment-0001.ksh>
Hello, As I understand it, the divide instructions are only available on the v7-R profile of the v7 architecture. Is that incorrect? -Jim On Dec 1, 2009, at 10:44 AM, Bagel wrote:> The thumb2 instructions include unsigned and signed divide. > Attached are a patch and test routine. > <div.diff><div.ll>_______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
I'm working with a Cortex-M3 core which is v7-M profile, and it has udiv and sdiv. bagel Jim Grosbach wrote: > Hello, > > As I understand it, the divide instructions are only available on the > v7-R profile of the v7 architecture. Is that incorrect? > > -Jim
Ah, ok. I was comparing v7-A and v7-R only. The M3 is described in separate documentation (mostly since it lacks the ARM mode instructions, I suspect). In any case, as far as I can tell, not all v7 processors support the hardware divide instructions. It's definitely desirable to support them for processors which do have them, but they need to be conditionalized such that they're only used when they're available. The instruction predicates are the best way to do that. For now, I would suggest adding a predicate such as "HasThumb2HardwareDivide" and hooking it up to a command line option to enable (see UseNEONFP in ARMSubTarget.cpp for an example of how to do that). You can then auto-enable it when the CPU string is "cortex- m3", as is done for the UseNEONFP option on the A8 (see the bottom of the ARMSubtarget::ARMSubtarget() constructor in ARMSubTarget.cpp). Thanks for looking at this! -Jim On Dec 1, 2009, at 12:12 PM, Bagel wrote:> I'm working with a Cortex-M3 core which is v7-M profile, and it has > udiv and sdiv. > > bagel > > Jim Grosbach wrote: >> Hello, >> >> As I understand it, the divide instructions are only available on the >> v7-R profile of the v7 architecture. Is that incorrect? >> >> -Jim > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
OK, here's a patch that follows your suggestion. I'm not an authorized developer, so I can't commit it myself. The test case is also attached again. bagel Jim Grosbach wrote: > Ah, ok. I was comparing v7-A and v7-R only. The M3 is described in > separate documentation (mostly since it lacks the ARM mode instructions, > I suspect). In any case, as far as I can tell, not all v7 processors > support the hardware divide instructions. > > It's definitely desirable to support them for processors which do have > them, but they need to be conditionalized such that they're only used > when they're available. The instruction predicates are the best way to > do that. For now, I would suggest adding a predicate such as > "HasThumb2HardwareDivide" and hooking it up to a command line option to > enable (see UseNEONFP in ARMSubTarget.cpp for an example of how to do > that). You can then auto-enable it when the CPU string is "cortex-m3", > as is done for the UseNEONFP option on the A8 (see the bottom of the > ARMSubtarget::ARMSubtarget() constructor in ARMSubTarget.cpp). > > Thanks for looking at this! > > -Jim -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: div-v2.diff URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091201/1b324257/attachment.ksh> -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: div.ll URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20091201/1b324257/attachment-0001.ksh>