similar to: [LLVMdev] thumb2 has divide instructions

I'm working with a Cortex-M3 core which is v7-M profile, and it has udiv and sdiv. bagel Jim Grosbach wrote: > Hello, > > As I understand it, the divide instructions are only available on the > v7-R profile of the v7 architecture. Is that incorrect? > > -Jim

OK, here's a patch that follows your suggestion. I'm not an authorized developer, so I can't commit it myself. The test case is also attached again. bagel Jim Grosbach wrote: > Ah, ok. I was comparing v7-A and v7-R only. The M3 is described in > separate documentation (mostly since it lacks the ARM mode instructions, > I suspect). In any case, as far as I can tell, not

Hello > OK, here's a patch that follows your suggestion.  I'm not an authorized > developer, so I can't commit it myself.  The test case is also attached > again. "T2Divide" should be a subtarget feature bit. This way it can be "automatically" assigned to the procesor. The instruction selection patterns for t2{S,U}DIV should be also guarded by this

Anton Korobeynikov wrote: > Hello > "T2Divide" should be a subtarget feature bit. This way it can be > "automatically" assigned to the procesor. I agree this is a better approach. > The instruction selection patterns for t2{S,U}DIV should be also > guarded by this predicate. Is this necessary? Since the absence of the predicate causes lowering to expand

When addresses are a displacement from a constant (this can happen in device drivers), the resulting address gets folded rather than using base+displacement addressing. This results in code bloat. Example test attached. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: const-addr.ll URL:

Here is a one-line patch to support the cortex-m3. For those who plan the features for ARM, the new cortex-m0 implements only a subset of the Thumb2 instructions. I still have yet to see a document that details what's in the subset. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: arm.diff URL:

Hello > Is this necessary?  Since the absence of the predicate causes lowering to > expand divides, the pattern should never show up. Just to guard codegen bugs. If anything went wrong (when predicates will be used) then you'll get nice assertion "cannot yet select". > Agreed.  Now how do we get this done? Just look how ArmV7A is defined and do something similar... --

Now that there is good thumb2 support in the ARM backend, would someone please add "cortex-m3" to the "-march" list for the ARM backend. This should produce pure thumb2 only code. At some point, when the subsets are public, "cortex-m1" and "cortex-m0" should also be added. thanks, bagel

Looks OK to me, but I don't have any Cortex-M3 docs to confirm the choice of v7-A without NEON. deep On Sun, Nov 22, 2009 at 9:47 PM, Bagel <bagel99 at gmail.com> wrote: > Here is a one-line patch to support the cortex-m3. > For those who plan the features for ARM, the new cortex-m0 implements only a > subset of the Thumb2 instructions.  I still have yet to see a document that

I'm not authorized to file bugs. Would someone please enter this? Thank you, bagel Evan Cheng wrote: > Right. I am aware of this problem but am not sure about what to do about it. > It's common for a number 32-bit immediates in the same block with the same > lower or higher 16-bit. Since the immediates will not be split until late in > codegen, the target independent

Is anyone working on supporting additional targets used in embedded systems. I am particularly interested in two: 1. TI MSP430. http://en.wikipedia.org/wiki/TI_MSP430 A nice very low power 16-bit machine with a PDP-11-like instruction set. We can assume the PIC16 developers have found and fixed all the 32-bit assumptions in the code base. Newer versions, the MSP430X series, have

On 22 July 2012 20:42, Anton Korobeynikov <anton at korobeynikov.info> wrote: >> Any suggestions? > Try to specify CPU explicitly. He shouldn't have to, but that might help. Maybe setting -march? This is a big mess... I thought that v7 always assumed Thumb2 for the thumb flag, and v7M should always assume Cortex-M3 CPU if none provided. It's funny that James had a great

On 23 July 2012 17:03, Chris Cadwallader <ccadwallader at arxan.com> wrote: > On Darwin, if -march is armv7 clang's driver will assume you want thumb2 unless you also give it -mno-thumb but that is irrelevant with mcpu=cortex-m3. I think that Thumb2 should be the default for v7 on any system, not just Darwin. Maybe some ARM folk can comment on this... -- cheers, --renato

When the IR specifies a 32 bit load can it be changed to a narrower load? What if the load is from memory (e.g. a peripheral) that only supports 32-bit access? Consider the following IR: ---- target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32" target triple = "thumbv7m-unknown-unknown" @f = external global i32 define zeroext i8 @bar() nounwind { L.0:

On 22 July 2012 22:03, salvatore benedetto <salvatore.benedetto at gmail.com> wrote: > While we are at it, if a new comer would like to understand where everything > takes place, where should he look? > > I did a grep in the source and eventually ended up in clang/something/driver. That's pretty much it: clang/lib/Driver

Hello, I'm trying to convince llc to compile into thumb2 ISA on ARMv7. I'm using: -march=thumb -mattr=v7,thumb2,vfp3 but llc complains about this with: llc: error: invalid target 'thumb -mattr=v7,thumb2,vfp3' I'm using LLVM from Aug 29 2011. To me the set of options looks sane so I'd like to ask what's wrong with this. Thanks! Karel

Assume an architecture that has multiple condition code registers, e.g., powerpc. Now assume that there are predicate instructions like thumb2, but can specify which condition code register they refer to. Now also assume that these predicate instructions themselves are predicatible, if executed they change the current predication state. Can LLVM handle multiple levels of predication? When is

Hi Karel, It actually looks like the argument parser has parsed "thumb -mattr=v7,thumb2,vfp3" as the full argument to "-march=". Strange. The easiest way to get what you want is probably "-mtriple thumbv7--". v7 has Thumb2 enabled and VFPv3 (along with NEON) by default. Cheers, James ________________________________________ From: llvmdev-bounces at cs.uiuc.edu

On Wed, Jul 18, 2012 at 6:08 PM, salvatore benedetto <salvatore.benedetto at gmail.com> wrote: > On Wed, Jul 18, 2012 at 5:45 PM, Renato Golin <rengolin at systemcall.org> wrote: >> On 18 July 2012 15:46, salvatore benedetto >> <salvatore.benedetto at gmail.com> wrote: >>> $ clang++ -ccc-host-triple thumbv7m-none-gnueabi noInclude.cpp -c >>>

On Darwin, if -march is armv7 clang's driver will assume you want thumb2 unless you also give it -mno-thumb but that is irrelevant with mcpu=cortex-m3. I agree its a mess. -Chris On Jul 22, 2012, at 4:37 PM, Renato Golin wrote: > On 22 July 2012 20:42, Anton Korobeynikov <anton at korobeynikov.info> wrote: >>> Any suggestions? >> Try to specify CPU explicitly. >