Displaying 20 results from an estimated 137 matches for "bagel".
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nagel
2010 Jul 12
3
Continuing on with a loop when there's a failure
Hi R sages,
Here is my latest problem. Consider the following toy example:
x <- read.table(textConnection("y1 y2 y3 x1 x2
indv.1 bagels donuts bagels 4 6
indv.2 donuts donuts donuts 5 1
indv.3 donuts donuts donuts 1 10
indv.4 donuts donuts donuts 10 9
indv.5 bagels donuts bagels 0 2
indv.6 bagels donuts bagels 2 9
indv.7 bagels donuts bagels 8 5
indv.8 bagels donuts bagels 4 1
indv.9 donuts donuts donuts 3 3
indv.10 bagels donuts...
2010 Jul 20
1
Nesting functions in loops that result in error messages breaking the loop
Hello all,
I am trying to write a program in R in which I call a function multiple
times within a loop. The problem is that sometimes the function breaks down
while calling another function, and produces an error message that breaks my
loop and the program stops. I would like to keep the loop running when this
function breaks down, and just move on to the next iteration in the loop.
Is there
2007 Dec 29
15
Do you think it would look cleaner?
I was looking over some of my specs.
I was thinking that the following:
@game.should_receive(:name).and_return(''The Battle for Blaze'')
@game.should_receive(:people).and_return(5000000)
@game.should_receive(:activated).and_return(true)
Would it look cleaner if I could do this instead?
@game.should_recieve_and_return(
:name => ''The Battle for Blaze''
2010 Sep 26
2
Splitting a data frame into several completely separate data frames
Hello again,
How do I split a data frame into smaller, completely separate data frames
(rather than separate data frames comprising a single "list")? Consider the
following data, and my coding attempt:
x <- read.table(textConnection("id type number
indv.1 bagel 6
indv.2 bagel 1
indv.3 donuts 10
indv.4 donuts 9"), header = TRUE)
closeAllConnections()
x.split <- split(x, x$type)
This is where I'm stuck. Now I have one "list" comprised of different data
frames, but what I want is separate data frames.
Ideally, I'd like to design...
2010 Jun 19
1
Extracting P-values from the lrm function in the rms library
Hello again R users,
I have a devilishly hard problem, which should be very simple. I hope someone out there will have the answer to this on the tip of their tongue.
Please consider the following toy example:
x <- read.table(textConnection("y x1 x2
indv.1 bagels 4 6
indv.2 donuts 5 1
indv.3 donuts 1 10
indv.4 donuts 10 9
indv.5 bagels 0 2
indv.6 bagels 2 9
indv.7 bagels 8 5
indv.8 bagels 4 1
indv.9 donuts 3 3
indv.10 bagels 5 9
indv.11 bagels 9 10
indv.12 bagels 3 1
indv.13 donuts 7 10
indv.14 bagels 2 10
indv.15 bagels 9 6"), header = TRUE)
I am fi...
2017 Feb 17
2
multiprecision add/sub
On 02/16/2017 12:08 PM, Stephen Canon wrote:
>> On Feb 16, 2017, at 9:12 AM, Bagel <bagel99 at gmail.com
>> <mailto:bagel99 at gmail.com>> wrote:
>>
>> I figured that the optimization of this would bedifficult (else it would
>> have already been done :-))
>
> Don’t make this assumption. There’s lots of opportunities for optimization
>...
2010 Nov 23
3
[LLVMdev] question on the status of debugging symbols
...I am on a linux x86-64 system (Fedora 13). Is gdb supposed to understand the
generated DWARF?
When I generate an executable with "clang -g" followed by "llc -O0" and feed it
to gdb, I get "no debugging symbols found".
What is the status of lldb on linux?
thanks,
bagel
2009 Aug 13
3
[LLVMdev] Branch Relaxation Support?
I think I have read that there are plans to generate object code (e.g. ELF)
directly in addition to assembly language source. If so, are there plans to
support branch relaxation for targets which support long/short branch
displacements? This is typically done in assemblers.
thanks,
bagel
2008 Mar 15
1
[LLVMdev] Question on use of subregs
Thanks, I seem to have gotten sub-registers to work. I can't seem to suppress
the zero-extend sometimes. There is no need to explicitly zero extend bytes to
words on this machine as all byte operations do that.
I have also gotten some memory-to-memory to work.
Bagel
Evan Cheng wrote:
> On Mar 14, 2008, at 10:17 AM, Bagel wrote:
>
>> I'm trying to write a backend for a machine that has both byte and
>> word
>> instructions. Both varieties of instructions operate on the same
>> set of
>> general registers. A byte m...
2016 Nov 10
3
array fill idioms
...t (which is
hard to express in C) something like
void foo () {
int bar[20] = { 42, 42, ..., 42 };
}
I don't want to do a memcopy of the 20 element constant array, and memset
doesn't work here. I want an intrinsic that copys the scalar int constant 42
to each element of the int array.
bagel
On 11/10/2016 03:30 PM, Mehdi Amini wrote:
> Hi,
>
> An alternative is to perform what is done for the equivalent C construct:
>
> void foo() {
> char bar[20] = “hello”;
> }
>
> ->
>
> @foo.bar = private unnamed_addr constant [20 x i8] c"hello\00\00\...
2010 Nov 24
0
[LLVMdev] question on the status of debugging symbols
On 23 November 2010 18:03, Bagel <bagel99 at gmail.com> wrote:
> Would someone be so kind as to tell me what the status of debugging symbols
> (DWARF) generated by clang/llvm is?
Hi Bagel,
It should be fairly complete...
> When I generate an executable with "clang -g" followed by "llc -O0" an...
2020 Mar 24
3
Questions on ifconversion and predication
Assume an architecture that has multiple condition code registers, e.g., powerpc.
Now assume that there are predicate instructions like thumb2, but can specify
which condition code register they refer to.
Now also assume that these predicate instructions themselves are predicatible,
if executed they change the current predication state.
Can LLVM handle multiple levels of predication?
When is
2017 Mar 07
2
multiprecision add/sub
...that doesn't have anything to do with multiprecision addition/subtraction. I am not aware of any way currently available to produce IR that will generate these nodes directly.
But what is the use case? What IR pattern it would replace?
—
Mehdi
>
> On Fri, Feb 17, 2017 at 8:52 PM, Bagel via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote:
> On 02/16/2017 12:08 PM, Stephen Canon wrote:
> >> On Feb 16, 2017, at 9:12 AM, Bagel <bagel99 at gmail.com <mailto:bagel99 at gmail.com>
> >> <mailto:bagel99 at gmail....
2010 Dec 04
4
[LLVMdev] question on generating dwarf metadata
...front-end can't use them because it is not
written in C or C++. I need to know the exact layouts of the LLVM
assembly metadata -- the textual form -- and what the fields mean. The
comments in your examples are close.
Perhaps you can add another section just on the textual format?
thanks, bagel
2008 Mar 14
2
[LLVMdev] Question on use of subregs
...registers are declared as SubRegs?
Also, this machine supports memory-to-memory operations in byte and word
flavors. What do I need to look out for to support this.
If have looked at the X86 *.td's, but that architecture is so complex it is
hard to extract the information I need.
Thanks,
Bagel
2004 May 19
0
Updated Fedora Core 2 Packages [unofficial]
...These packages were compiled on a freshly-installed Fedora Core 2 box, and
they were tested to work correctly with winbind Active Directory user
authentication. The `winbind -t` command gives beautiful results, now.
These unofficial packages are now available from the following location:
ftp://bagel.express.org/fedora/core2-packages
/samba/samba-3.0.4-4.wrl.src.rpm
ftp://bagel.express.org/fedora/core2-packages
/samba/samba-3.0.4-4.wrl.i386.rpm
ftp://bagel.express.org/fedora/core2-packages
/samba/samba-client-3.0.4-4.wrl.i386.rpm
ftp://bagel.express.org/fedora/core2-packages...
2011 Jun 24
2
[LLVMdev] multiple return value assembler regression?
On 06/24/2011 03:45 PM, Chris Lattner wrote:
>
> On Jun 24, 2011, at 9:29 AM, Bagel wrote:
>
>> It appears the syntax for returning multiple values has changed since 2.9.
>> Previous to that:
>> ret i32 %a, i32 %b
>> worked. The new syntax is something like:
>> ret { i32, i32 }{i32 %a, i32 %b}
>> but this yields an error:
>> mrv-bu...
2015 Jul 17
3
[LLVMdev] 2-address and 3-address instructions
...if a mov reg-to-reg proceeds or follows a 2-address instruction and turn
it into a 3-address version?
3. Or do I generate 3-address and have a custom pass that checks if a source
and destination register in a 3-address is the same and turn it into a 2-address?
Anybody done this already?
Thanks,
Bagel
2010 Dec 06
4
[LLVMdev] question on generating dwarf metadata
...ctions that return multiple
values (as does my language), and DW_TAG_subroutine_type implementation
currently supports, at most, a single returned value, this might be a bug.
Looking at the code in lib/CodeGen/AsmPrinter/DwarfDebug.cpp around line 1035,
this does appear to be the case.
thanks, bagel
2008 Mar 14
0
[LLVMdev] Question on use of subregs
On Mar 14, 2008, at 10:17 AM, Bagel wrote:
> I'm trying to write a backend for a machine that has both byte and
> word
> instructions. Both varieties of instructions operate on the same
> set of
> general registers. A byte mode instruction on a general register
> always clears
> the upper bits. Regi...