search for: v7m

Displaying 20 results from an estimated 26 matches for "v7m".

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2010 Nov 27
1
[LLVMdev] Patch for V7M
Hello All, Attached is a patch for the ARM target. The ARM v7M profile does not have the signed most-significant-word multiply instruction so SMMUL, for instance, is not valid on Cortex-M3 and Cortex-M4. The attached patch adds an additional attribute, +mmul, which controls most-significant word multiplies on v6T2+ targets. This is especially impo...
2014 Dec 16
1
[LLVMdev] Newbee question: LLVM backend regression tests for thumb1 targets on simulator possible?
...r the most part, unless you emit thumb2 > instructions (which will work on cortex-m3, but not m0). The list of > them is pretty small though IIRC, so maybe you can write a script that > disassembles & checks for them. Cortex-M0 implements the v6m architecture. Cortex-M3 implements the v7m architecture. Having had a quick look at the v6m and the v7m ARMARM's, next to the extra instructions v7m supports, I think the main other difference that's very relevant for a code generator is that v6m always generates a fault when an unaligned access occurs, whereas v7m can support unal...
2009 Dec 02
2
[LLVMdev] thumb2 has divide instructions
...oach. > The instruction selection patterns for t2{S,U}DIV should be also > guarded by this predicate. Is this necessary? Since the absence of the predicate causes lowering to expand divides, the pattern should never show up. > > Also, for cortex-m3 it will be nice to have separate V7M feature profile. > Agreed. Now how do we get this done? regards, bagel
2015 Nov 21
2
Recent -Os code size regressions
...; Hi Steve, > > I still haven't got around doing a CI for EEMBC or SPEC on ARM. I do > track performance every release, but not code size at -Os. > >> I've noticed troubling regressions lately. Sometime near Nov >> 5, the EEMBC bitmnp01 benchmark grew by 25% for ARMv7m and 35% for >> i586. That's ghastly. This week, the EEMBC matrix01 workload grew by >> 5% for ARMv7m and 3% for i586. > > Hum, v7M is even lower priority for me at the moment. :) > > Though, I have to say, 25% is really bad. Can you bisect to see which > commit was...
2012 Jul 22
12
[LLVMdev] Setting up a cross-compiler for cortex-m3
...22 July 2012 20:42, Anton Korobeynikov <anton at korobeynikov.info> wrote: >> Any suggestions? > Try to specify CPU explicitly. He shouldn't have to, but that might help. Maybe setting -march? This is a big mess... I thought that v7 always assumed Thumb2 for the thumb flag, and v7M should always assume Cortex-M3 CPU if none provided. It's funny that James had a great patch to solve all those problems by implementing Clang's architecture selection in table-gen more than an year ago. I wonder what happened to that thread... :/ -- cheers, --renato http://systemcall.o...
2009 Dec 01
2
[LLVMdev] thumb2 has divide instructions
OK, here's a patch that follows your suggestion. I'm not an authorized developer, so I can't commit it myself. The test case is also attached again. bagel Jim Grosbach wrote: > Ah, ok. I was comparing v7-A and v7-R only. The M3 is described in > separate documentation (mostly since it lacks the ARM mode instructions, > I suspect). In any case, as far as I can tell, not
2009 Dec 01
0
[LLVMdev] thumb2 has divide instructions
...also attached > again. "T2Divide" should be a subtarget feature bit. This way it can be "automatically" assigned to the procesor. The instruction selection patterns for t2{S,U}DIV should be also guarded by this predicate. Also, for cortex-m3 it will be nice to have separate V7M feature profile. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University
2009 Dec 02
0
[LLVMdev] thumb2 has divide instructions
Hello > Is this necessary?  Since the absence of the predicate causes lowering to > expand divides, the pattern should never show up. Just to guard codegen bugs. If anything went wrong (when predicates will be used) then you'll get nice assertion "cannot yet select". > Agreed.  Now how do we get this done? Just look how ArmV7A is defined and do something similar... --
2015 Nov 19
2
Recent -Os code size regressions
Hello LLVM, Does the community have bots or humans tracking code size for -Os builds? I've noticed troubling regressions lately. Sometime near Nov 5, the EEMBC bitmnp01 benchmark grew by 25% for ARMv7m and 35% for i586. That's ghastly. This week, the EEMBC matrix01 workload grew by 5% for ARMv7m and 3% for i586. Regards, -steve
2015 Nov 21
3
Recent -Os code size regressions
...; Hi Steve, > > I still haven't got around doing a CI for EEMBC or SPEC on ARM. I do > track performance every release, but not code size at -Os. > >> I've noticed troubling regressions lately. Sometime near Nov >> 5, the EEMBC bitmnp01 benchmark grew by 25% for ARMv7m and 35% for >> i586. That's ghastly. This week, the EEMBC matrix01 workload grew by >> 5% for ARMv7m and 3% for i586. > > Hum, v7M is even lower priority for me at the moment. :) > > Though, I have to say, 25% is really bad. Can you bisect to see which > commit was...
2012 Jul 22
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
> Any suggestions? Try to specify CPU explicitly. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University
2012 Jul 22
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
...eynikov <anton at korobeynikov.info> wrote: >>> Any suggestions? >> Try to specify CPU explicitly. > > He shouldn't have to, but that might help. Maybe setting -march? This > is a big mess... > > I thought that v7 always assumed Thumb2 for the thumb flag, and v7M > should always assume Cortex-M3 CPU if none provided. > > It's funny that James had a great patch to solve all those problems by > implementing Clang's architecture selection in table-gen more than an > year ago. I wonder what happened to that thread... :/ While we are at i...
2012 Jul 23
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
...nikov <anton at korobeynikov.info> wrote: >>> Any suggestions? >> Try to specify CPU explicitly. > > He shouldn't have to, but that might help. Maybe setting -march? This > is a big mess... > > I thought that v7 always assumed Thumb2 for the thumb flag, and v7M > should always assume Cortex-M3 CPU if none provided. > > It's funny that James had a great patch to solve all those problems by > implementing Clang's architecture selection in table-gen more than an > year ago. I wonder what happened to that thread... :/ > > -- &g...
2012 Jul 24
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
...> Making Thumb2 the default for any ARMv7 triple, on the other hand, is a change that could be made in a matter of minutes. > > It's not that simple. That defaults Thumb for v7 architectures, which > means armv7 and thumbv7 would be the same. A better fix would be to > make thumbv7m to actually produce the correct thumb code! > The question was how to get the same behavior as on Darwin. I pointed at the code that does this for Darwin. I make no claims that the code there, or anywhere else in Driver, for that matter, is anything resembling a paragon of fine design. That wa...
2013 Oct 11
3
[LLVMdev] Generate code for ARM Cortex m0, m3, and m4.
...i, I am trying to cross compile code for ARM Cortex m0, m3, and m4. For m0, I use: -target armv6--eabi -mcpu=cortex-m0 That seems to work. For m3 and m4, I use the following which does not work (fatal error: error in backend: CPU: 'cortex-m3' does not support ARM mode): -target armv7m--eabi -mcpu=cortex-m3 and -target armv7em--eabi -mcpu=cortex-m4 Who can help me with the right command line arguments for m3 and m4? Thanks, Jan
2012 Jul 23
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
On Sun, Jul 22, 2012 at 11:12 PM, Renato Golin <rengolin at systemcall.org> wrote: > On 22 July 2012 22:03, salvatore benedetto > <salvatore.benedetto at gmail.com> wrote: >> While we are at it, if a new comer would like to understand where everything >> takes place, where should he look? >> >> I did a grep in the source and eventually ended up in
2012 Jul 22
3
[LLVMdev] Setting up a cross-compiler for cortex-m3
...etto <salvatore.benedetto at gmail.com> wrote: > On Wed, Jul 18, 2012 at 5:45 PM, Renato Golin <rengolin at systemcall.org> wrote: >> On 18 July 2012 15:46, salvatore benedetto >> <salvatore.benedetto at gmail.com> wrote: >>> $ clang++ -ccc-host-triple thumbv7m-none-gnueabi noInclude.cpp -c >>> --sysroot=/home/emitrax/CodeSourcery/Sourcery_G++_Lite/arm-none-linux-gnueabi/libc/ >> >> Try -ccc-gcc-name arm-none-linux-gnueabi-g++ -ccc-host-triple >> thumbv7m-none-linux-gnueabi >> >> Sometimes it's better than sysroo...
2012 Jul 24
0
[LLVMdev] Setting up a cross-compiler for cortex-m3
On Jul 23, 2012, at 1:52 PM, salvatore benedetto <salvatore.benedetto at gmail.com> wrote: > On Mon, Jul 23, 2012 at 8:14 PM, Renato Golin <rengolin at systemcall.org> wrote: >> On 23 July 2012 17:03, Chris Cadwallader <ccadwallader at arxan.com> wrote: >>> On Darwin, if -march is armv7 clang's driver will assume you want thumb2 unless you also give it
2014 Jul 09
5
[LLVMdev] [PATCH][REQUEST] Could someone submit this CSR Kalimba definitions patch please?
...// SPIR: standard portable IR for OpenCL 64-bit version + spir64, // SPIR: standard portable IR for OpenCL 64-bit version + kalimba // Kalimba: generic kalimba }; - enum SubArchType { - NoSubArch, - - ARMSubArch_v8, - ARMSubArch_v7, - ARMSubArch_v7em, - ARMSubArch_v7m, - ARMSubArch_v7s, - ARMSubArch_v6, - ARMSubArch_v6m, - ARMSubArch_v6t2, - ARMSubArch_v5, - ARMSubArch_v5te, - ARMSubArch_v4t, - ARMSubArch_v4 - }; enum VendorType { UnknownVendor, @@ -104,7 +89,8 @@ BGQ, Freescale, IBM, - NVIDIA + NVIDIA,...
2012 Jul 22
3
[LLVMdev] Setting up a cross-compiler for cortex-m3
On 22 July 2012 22:03, salvatore benedetto <salvatore.benedetto at gmail.com> wrote: > While we are at it, if a new comer would like to understand where everything > takes place, where should he look? > > I did a grep in the source and eventually ended up in clang/something/driver. That's pretty much it: clang/lib/Driver