Ok, I've had time to track this down a little bit more and I seem to
have found another case where it fails. This is occurring during
Schedulur->EmitSchedule() in SelectionDAGISel.cpp:695. The problem seems
to be that somehow the CopyToReg part of the switch statement in
ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is
especially problematic because the code is either expecting a
VirtualRegister or a RegisterSDNode in this location. I've checked all
locations where I use the DAG.getCopyToReg function and none of them
pass in a frameindex. I explcitily check that I have a register before
passing in the value to Register number to CopyToReg, so this leads me
to believe that it is being generated somehow by LLVM.
In the case I sent earlier in this thread it only occurs when I turn
optimizations on, but the new case I hit with optimizations off but
through a different method.
I've tried the strip-debug method and that doesn't seem to help, any
other ideas or tips where I can look to further debug this issue would
be very helpful.
Thanks,
Micah
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Bill Wendling
Sent: Thursday, January 15, 2009 3:32 PM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Hitting assertion, unsure why
Other than not using debugging ('-g' and the like), not really. :-( I
think that Devang is actively working on fixing this, though. It might
not be too much longer.
-bw
On Thu, Jan 15, 2009 at 3:26 PM, Villmow, Micah <Micah.Villmow at amd.com>
wrote:> This did not seem to work, any other ideas?
>
> Thanks,
>
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
cs.uiuc.edu]
> On Behalf Of Bill Wendling
> Sent: Thursday, January 15, 2009 2:26 PM
> To: LLVM Developers Mailing List
> Subject: Re: [LLVMdev] Hitting assertion, unsure why
>
> Don't generate debug info at this time (you can use "opt
> -strip-debug")? :-) Otherwise, I'm not sure.
>
> -bw
>
> On Thu, Jan 15, 2009 at 2:20 PM, Villmow, Micah
<Micah.Villmow at amd.com>> wrote:
>> Is there any known method/hack of bypassing this?
>>
>> Thanks,
>>
>> -----Original Message-----
>> From: llvmdev-bounces at cs.uiuc.edu
[mailto:llvmdev-bounces at cs.uiuc.edu]>> On Behalf Of Bill Wendling
>> Sent: Thursday, January 15, 2009 2:07 PM
>> To: LLVM Developers Mailing List
>> Subject: Re: [LLVMdev] Hitting assertion, unsure why
>>
>> On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah
> <Micah.Villmow at amd.com>
>> wrote:
>>> I am hitting this assertion:
>>>
>>> assert(I != VRBaseMap.end() && "Node emitted out of
order - late");
>>>
>>> I am not sure why this assertion is being triggered or what I
changed>> that
>>> is causing it.
>>>
>>> This is asserting when SDValue is FrameIndexSDNode 1.
>>>
>>> I don't have any code that modified frameindices until my
overloaded
>>> RegisterInfo function.
>>>
>>> I've attached the bc file. If I generate an unoptimized bc file
then
>> there
>>> is no issue, only when I turn optimizations on do I hit this
problem.>>>
>> I got this too. It's related to debug information being in flux
right
>> now. I believe that Devang is working on a fix for this right now.
>>
>> -bw
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
>
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
_______________________________________________
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LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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On Jan 27, 2009, at 3:54 PM, Villmow, Micah wrote:> Ok, I've had time to track this down a little bit more and I seem to > have found another case where it fails. This is occurring during > Schedulur->EmitSchedule() in SelectionDAGISel.cpp:695. The problem > seems > to be that somehow the CopyToReg part of the switch statement in > ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is > especially problematic because the code is either expecting a > VirtualRegister or a RegisterSDNode in this location. I've checked allUnfortunately, I don't think anyone can help you until you can track down what is creating the FrameIndex. Why not set a break point in MachineFrameInfo::CreateFixedObject and CreateStackObject? Evan> > locations where I use the DAG.getCopyToReg function and none of them > pass in a frameindex. I explcitily check that I have a register before > passing in the value to Register number to CopyToReg, so this leads me > to believe that it is being generated somehow by LLVM. > > In the case I sent earlier in this thread it only occurs when I turn > optimizations on, but the new case I hit with optimizations off but > through a different method. > > I've tried the strip-debug method and that doesn't seem to help, any > other ideas or tips where I can look to further debug this issue would > be very helpful. > > Thanks, > Micah > > > > > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Bill Wendling > Sent: Thursday, January 15, 2009 3:32 PM > To: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Hitting assertion, unsure why > > Other than not using debugging ('-g' and the like), not really. :-( I > think that Devang is actively working on fixing this, though. It might > not be too much longer. > > -bw > > On Thu, Jan 15, 2009 at 3:26 PM, Villmow, Micah > <Micah.Villmow at amd.com> > wrote: >> This did not seem to work, any other ideas? >> >> Thanks, >> >> -----Original Message----- >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev- >> bounces at cs.uiuc.edu] >> On Behalf Of Bill Wendling >> Sent: Thursday, January 15, 2009 2:26 PM >> To: LLVM Developers Mailing List >> Subject: Re: [LLVMdev] Hitting assertion, unsure why >> >> Don't generate debug info at this time (you can use "opt >> -strip-debug")? :-) Otherwise, I'm not sure. >> >> -bw >> >> On Thu, Jan 15, 2009 at 2:20 PM, Villmow, Micah > <Micah.Villmow at amd.com> >> wrote: >>> Is there any known method/hack of bypassing this? >>> >>> Thanks, >>> >>> -----Original Message----- >>> From: llvmdev-bounces at cs.uiuc.edu > [mailto:llvmdev-bounces at cs.uiuc.edu] >>> On Behalf Of Bill Wendling >>> Sent: Thursday, January 15, 2009 2:07 PM >>> To: LLVM Developers Mailing List >>> Subject: Re: [LLVMdev] Hitting assertion, unsure why >>> >>> On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah >> <Micah.Villmow at amd.com> >>> wrote: >>>> I am hitting this assertion: >>>> >>>> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >>>> >>>> I am not sure why this assertion is being triggered or what I > changed >>> that >>>> is causing it. >>>> >>>> This is asserting when SDValue is FrameIndexSDNode 1. >>>> >>>> I don't have any code that modified frameindices until my >>>> overloaded >>>> RegisterInfo function. >>>> >>>> I've attached the bc file. If I generate an unoptimized bc file >>>> then >>> there >>>> is no issue, only when I turn optimizations on do I hit this > problem. >>>> >>> I got this too. It's related to debug information being in flux >>> right >>> now. I believe that Devang is working on a fix for this right now. >>> >>> -bw >>> _______________________________________________ >>> LLVM Developers mailing list >>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >>> >>> >>> >>> _______________________________________________ >>> LLVM Developers mailing list >>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >>> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> >> >> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > < > StandardLinkConstraintSet > .bc>_______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Evan, Thanks for the tip, I was able to track down where the FrameIndex is being created and I think I know where the problem is now. Micah -----Original Message----- From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Evan Cheng Sent: Wednesday, January 28, 2009 9:18 AM To: LLVM Developers Mailing List Subject: Re: [LLVMdev] Hitting assertion, unsure why On Jan 27, 2009, at 3:54 PM, Villmow, Micah wrote:> Ok, I've had time to track this down a little bit more and I seem to > have found another case where it fails. This is occurring during > Schedulur->EmitSchedule() in SelectionDAGISel.cpp:695. The problem > seems > to be that somehow the CopyToReg part of the switch statement in > ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is > especially problematic because the code is either expecting a > VirtualRegister or a RegisterSDNode in this location. I've checked allUnfortunately, I don't think anyone can help you until you can track down what is creating the FrameIndex. Why not set a break point in MachineFrameInfo::CreateFixedObject and CreateStackObject? Evan> > locations where I use the DAG.getCopyToReg function and none of them > pass in a frameindex. I explcitily check that I have a register before > passing in the value to Register number to CopyToReg, so this leads me > to believe that it is being generated somehow by LLVM. > > In the case I sent earlier in this thread it only occurs when I turn > optimizations on, but the new case I hit with optimizations off but > through a different method. > > I've tried the strip-debug method and that doesn't seem to help, any > other ideas or tips where I can look to further debug this issue would > be very helpful. > > Thanks, > Micah > > > > > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Bill Wendling > Sent: Thursday, January 15, 2009 3:32 PM > To: LLVM Developers Mailing List > Subject: Re: [LLVMdev] Hitting assertion, unsure why > > Other than not using debugging ('-g' and the like), not really. :-( I > think that Devang is actively working on fixing this, though. It might > not be too much longer. > > -bw > > On Thu, Jan 15, 2009 at 3:26 PM, Villmow, Micah > <Micah.Villmow at amd.com> > wrote: >> This did not seem to work, any other ideas? >> >> Thanks, >> >> -----Original Message----- >> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev- >> bounces at cs.uiuc.edu] >> On Behalf Of Bill Wendling >> Sent: Thursday, January 15, 2009 2:26 PM >> To: LLVM Developers Mailing List >> Subject: Re: [LLVMdev] Hitting assertion, unsure why >> >> Don't generate debug info at this time (you can use "opt >> -strip-debug")? :-) Otherwise, I'm not sure. >> >> -bw >> >> On Thu, Jan 15, 2009 at 2:20 PM, Villmow, Micah > <Micah.Villmow at amd.com> >> wrote: >>> Is there any known method/hack of bypassing this? >>> >>> Thanks, >>> >>> -----Original Message----- >>> From: llvmdev-bounces at cs.uiuc.edu > [mailto:llvmdev-bounces at cs.uiuc.edu] >>> On Behalf Of Bill Wendling >>> Sent: Thursday, January 15, 2009 2:07 PM >>> To: LLVM Developers Mailing List >>> Subject: Re: [LLVMdev] Hitting assertion, unsure why >>> >>> On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah >> <Micah.Villmow at amd.com> >>> wrote: >>>> I am hitting this assertion: >>>> >>>> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >>>> >>>> I am not sure why this assertion is being triggered or what I > changed >>> that >>>> is causing it. >>>> >>>> This is asserting when SDValue is FrameIndexSDNode 1. >>>> >>>> I don't have any code that modified frameindices until my >>>> overloaded >>>> RegisterInfo function. >>>> >>>> I've attached the bc file. If I generate an unoptimized bc file >>>> then >>> there >>>> is no issue, only when I turn optimizations on do I hit this > problem. >>>> >>> I got this too. It's related to debug information being in flux >>> right >>> now. I believe that Devang is working on a fix for this right now. >>> >>> -bw >>> _______________________________________________ >>> LLVM Developers mailing list >>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >>> >>> >>> >>> _______________________________________________ >>> LLVM Developers mailing list >>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >>> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> >> >> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >> > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > < > StandardLinkConstraintSet > .bc>_______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev_______________________________________________ LLVM Developers mailing list LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Well, I thought I knew how to fix the problem, but it seems my changes
didn't help at all. The frame index is being created when
FuncInfo->set() is called in SelectionDAGISel::runOnFunction().
This occurs at line 293 in SelectionDAGBuild.cpp when dealing with the
alloca instructions.
I've found the CopyToReg that is being issued occurs in LowerCALL and it
is this one that fails. When I get the arguments to the function call,
(SDValue Arg = TheCall->getArg(i);), the returned SDValue is a
FrameIndex, and I don't handle the case correctly. The only issue that I
have is that none of the other backends have any code in
LowerCALL/LowerRET/LowerFORMAL_ARGUMENTS that explicitly handle
FrameIndexSDNode's as arguments. This leads me to believe that I
shouldn't have to handle this case and there is an error occurring
somewhere else and is showing up here.
My test case is fairly simple:
float func(float *a);
void test(float *positions)
{
float linkABNorm = positions[0];
float b = func(&linkABNorm);
positions[0] = b * linkABNorm;
}
float func(float *a)
{
*a = 10.0f;
return *a;
}
The problem is linked to taking the address of the stack variable and
passing it as a pointer to another function.
So, my questions are:
1) Is there anything special I should be doing to handle a
FrameIndexSDNode being passed into LowerCALL?
2) If not, Where can I look that might show some light on what I'm doing
wrong in tablegen/ISelLowering?
3) What is the expected behavior of llvm in this case?
Thanks for any help,
Micah
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
On Behalf Of Evan Cheng
Sent: Wednesday, January 28, 2009 9:18 AM
To: LLVM Developers Mailing List
Subject: Re: [LLVMdev] Hitting assertion, unsure why
On Jan 27, 2009, at 3:54 PM, Villmow, Micah wrote:
> Ok, I've had time to track this down a little bit more and I seem to
> have found another case where it fails. This is occurring during
> Schedulur->EmitSchedule() in SelectionDAGISel.cpp:695. The problem
> seems
> to be that somehow the CopyToReg part of the switch statement in
> ScheduleDAG::EmitNode has a FrameIndex as its second operand. This is
> especially problematic because the code is either expecting a
> VirtualRegister or a RegisterSDNode in this location. I've checked all
Unfortunately, I don't think anyone can help you until you can track
down what is creating the FrameIndex. Why not set a break point in
MachineFrameInfo::CreateFixedObject and CreateStackObject?
Evan
>
> locations where I use the DAG.getCopyToReg function and none of them
> pass in a frameindex. I explcitily check that I have a register before
> passing in the value to Register number to CopyToReg, so this leads me
> to believe that it is being generated somehow by LLVM.
>
> In the case I sent earlier in this thread it only occurs when I turn
> optimizations on, but the new case I hit with optimizations off but
> through a different method.
>
> I've tried the strip-debug method and that doesn't seem to help,
any
> other ideas or tips where I can look to further debug this issue would
> be very helpful.
>
> Thanks,
> Micah
>
>
>
>
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
cs.uiuc.edu]
> On Behalf Of Bill Wendling
> Sent: Thursday, January 15, 2009 3:32 PM
> To: LLVM Developers Mailing List
> Subject: Re: [LLVMdev] Hitting assertion, unsure why
>
> Other than not using debugging ('-g' and the like), not really. :-(
I
> think that Devang is actively working on fixing this, though. It might
> not be too much longer.
>
> -bw
>
> On Thu, Jan 15, 2009 at 3:26 PM, Villmow, Micah
> <Micah.Villmow at amd.com>
> wrote:
>> This did not seem to work, any other ideas?
>>
>> Thanks,
>>
>> -----Original Message-----
>> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-
>> bounces at cs.uiuc.edu]
>> On Behalf Of Bill Wendling
>> Sent: Thursday, January 15, 2009 2:26 PM
>> To: LLVM Developers Mailing List
>> Subject: Re: [LLVMdev] Hitting assertion, unsure why
>>
>> Don't generate debug info at this time (you can use "opt
>> -strip-debug")? :-) Otherwise, I'm not sure.
>>
>> -bw
>>
>> On Thu, Jan 15, 2009 at 2:20 PM, Villmow, Micah
> <Micah.Villmow at amd.com>
>> wrote:
>>> Is there any known method/hack of bypassing this?
>>>
>>> Thanks,
>>>
>>> -----Original Message-----
>>> From: llvmdev-bounces at cs.uiuc.edu
> [mailto:llvmdev-bounces at cs.uiuc.edu]
>>> On Behalf Of Bill Wendling
>>> Sent: Thursday, January 15, 2009 2:07 PM
>>> To: LLVM Developers Mailing List
>>> Subject: Re: [LLVMdev] Hitting assertion, unsure why
>>>
>>> On Thu, Jan 15, 2009 at 1:54 PM, Villmow, Micah
>> <Micah.Villmow at amd.com>
>>> wrote:
>>>> I am hitting this assertion:
>>>>
>>>> assert(I != VRBaseMap.end() && "Node emitted out
of order - late");
>>>>
>>>> I am not sure why this assertion is being triggered or what I
> changed
>>> that
>>>> is causing it.
>>>>
>>>> This is asserting when SDValue is FrameIndexSDNode 1.
>>>>
>>>> I don't have any code that modified frameindices until my
>>>> overloaded
>>>> RegisterInfo function.
>>>>
>>>> I've attached the bc file. If I generate an unoptimized bc
file
>>>> then
>>> there
>>>> is no issue, only when I turn optimizations on do I hit this
> problem.
>>>>
>>> I got this too. It's related to debug information being in flux
>>> right
>>> now. I believe that Devang is working on a fix for this right now.
>>>
>>> -bw
>>> _______________________________________________
>>> LLVM Developers mailing list
>>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>>
>>>
>>>
>>> _______________________________________________
>>> LLVM Developers mailing list
>>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>>
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>>
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
> <
> StandardLinkConstraintSet
> .bc>_______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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