search for: frameindexsdnode

...urs with regular old pointer-allocas.) The exception I am getting occurs in this code here in SelectionDAGBuilder.cpp: *case* *Intrinsic*::gcroot: *if* (GFI) { *const* Value *Alloca = I.getArgOperand(0); *const* Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); * FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());* GFI->addStackRoot(FI->getIndex(), TypeMap); } *return* 0; Specifically, the cast from SDNode to FrameIndexSDNode fails because the node type is DYNAMIC_STACKALLOC, while this code is expecting the node type to be "...

...:LowerArguments SDB->setValue(&Arg, Res); if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex()); } Is it in BUG or am I missing something? Thanks, Yaniv

I'm trying to track down the problem with the assertion failure in SelectionDAGBuilder.cpp. This is the code: *case* *Intrinsic*::gcroot: *if* (GFI) { *const* Value *Alloca = I.getArgOperand(0); *const* Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); * FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());* GFI->addStackRoot(FI->getIndex(), TypeMap); } *return* 0 The cast<FrameIndexSDNode> is what's failing. Apparently the node isn't a FrameIndexSDNode. Now, we discussed a similar problem on this list earlie...

...etInstrInfo::IMPLICIT_DEF || + MI->getOpcode() == TargetInstrInfo::DECLARE) return 0; Same for ARM::DBG_LABEL. 3. + case ISD::DECLARE: { + SDValue Chain = Op.getOperand(0); + SDValue N1 = Op.getOperand(1); + SDValue N2 = Op.getOperand(2); + + if (!isa<FrameIndexSDNode>(N1)) + break; + + int FI = cast<FrameIndexSDNode>(N1)->getIndex(); Something like this will be better: FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1); if (!FINode) break; int FI = FINode->getIndex(); I'll fix these minor...

...; The exception I am getting occurs in this code here in > SelectionDAGBuilder.cpp: > > *case* *Intrinsic*::gcroot: > > *if* (GFI) { > *const* Value *Alloca = I.getArgOperand(0); > *const* Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); > * FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());* GFI->addStackRoot(FI->getIndex(), TypeMap); > } > *return* 0; > > Specifically, the cast from SDNode to FrameIndexSDNode fails because the > node type is DYNAMIC_STACKALLOC, while this code is expecti...

...ecided not to bother with stack register yet and instead I just emit FrameIndex as immediate: bool MyBackendDAGToDAGISel::SelectAddrFI(SDValue &N, SDValue &R) { if (N.getOpcode() != ISD::FrameIndex) return false; MachineFrameInfo &MFI = MF->getFrameInfo(); int FX = cast<FrameIndexSDNode>(N)->getIndex(); R = CurDAG->getTargetFrameIndex(FX, MVT::i32); return true; } This way I end up with store %r1, [1] and handle it in my CPU emulator accordingly. So, instead of matching that FrameIndex in store, I really want to emit a load first and then use a register in the sto...

...false, false, 0); “ I have two questions here: (1) should I return some merges values( returnValue, DstValue) ? or only return returnValue is right? ( the dag dumped out looks better if I return the merged values) (2) How the FrameIndex should be computed? I use DAG.getFrameIndex((dyn_cast<FrameIndexSDnode>( frindex.getNode()))->getIndex(), i32), not confident it is correct, any good examples to understand to this? Best Kevin -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140729/cb44e46b/attachment.htm...

Hi all, FlexyCore, the company I am working for, use LLVM to generate binary for ARM platform. We are very fulfilled with LLVM, and FlexyCore will be pleased to contribute on this software. We need debug support in ARM binary, but, in LLVM 2.4, this support is not activated for ARM backend. Consequently, I made small modifications in order to activate it (see the patch in attach file). My

I am hitting this assertion: assert(I != VRBaseMap.end() && "Node emitted out of order - late"); I am not sure why this assertion is being triggered or what I changed that is causing it. This is asserting when SDValue is FrameIndexSDNode 1. I don't have any code that modified frameindices until my overloaded RegisterInfo function. I've attached the bc file. If I generate an unoptimized bc file then there is no issue, only when I turn optimizations on do I hit this problem. Thanks for any hints, Micah Villmow...

...the arguments to the function call, (SDValue Arg = TheCall->getArg(i);), the returned SDValue is a FrameIndex, and I don't handle the case correctly. The only issue that I have is that none of the other backends have any code in LowerCALL/LowerRET/LowerFORMAL_ARGUMENTS that explicitly handle FrameIndexSDNode's as arguments. This leads me to believe that I shouldn't have to handle this case and there is an error occurring somewhere else and is showing up here. My test case is fairly simple: float func(float *a); void test(float *positions) { float linkABNorm = positions[0]; float b = func(&a...

...t amd.com> wrote: > I am hitting this assertion: > > assert(I != VRBaseMap.end() && "Node emitted out of order - late"); > > I am not sure why this assertion is being triggered or what I changed that > is causing it. > > This is asserting when SDValue is FrameIndexSDNode 1. > > I don't have any code that modified frameindices until my overloaded > RegisterInfo function. > > I've attached the bc file. If I generate an unoptimized bc file then there > is no issue, only when I turn optimizations on do I hit this problem. > I got this too....

...t amd.com> wrote: > I am hitting this assertion: > > assert(I != VRBaseMap.end() && "Node emitted out of order - late"); > > I am not sure why this assertion is being triggered or what I changed that > is causing it. > > This is asserting when SDValue is FrameIndexSDNode 1. > > I don't have any code that modified frameindices until my overloaded > RegisterInfo function. > > I've attached the bc file. If I generate an unoptimized bc file then there > is no issue, only when I turn optimizations on do I hit this problem. > I got this too....

...t; >>> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >>> >>> I am not sure why this assertion is being triggered or what I changed >> that >>> is causing it. >>> >>> This is asserting when SDValue is FrameIndexSDNode 1. >>> >>> I don't have any code that modified frameindices until my overloaded >>> RegisterInfo function. >>> >>> I've attached the bc file. If I generate an unoptimized bc file then >> there >>> is no issue, only when I turn opti...

...RBaseMap.end() && "Node emitted out of order - late"); >>>> >>>> I am not sure why this assertion is being triggered or what I > changed >>> that >>>> is causing it. >>>> >>>> This is asserting when SDValue is FrameIndexSDNode 1. >>>> >>>> I don't have any code that modified frameindices until my >>>> overloaded >>>> RegisterInfo function. >>>> >>>> I've attached the bc file. If I generate an unoptimized bc file >>>> then >...

..., N1); I checked visitADD more and find that it performs some kind of undo like bellow if the input is (+ (+ FI <const>) <const>). // Undo the add -> or combine to merge constant offsets from a frame index. if (N0.getOpcode() == ISD::OR && isa<FrameIndexSDNode>(N0.getOperand(0)) && isa<ConstantSDNode>(N0.getOperand(1)) && DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) { SDValue Add0 = DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(1)); return DAG.getNode(ISD::ADD, DL, VT,...

...tting this assertion: >> >> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >> >> I am not sure why this assertion is being triggered or what I changed > that >> is causing it. >> >> This is asserting when SDValue is FrameIndexSDNode 1. >> >> I don't have any code that modified frameindices until my overloaded >> RegisterInfo function. >> >> I've attached the bc file. If I generate an unoptimized bc file then > there >> is no issue, only when I turn optimizations on do I hit this p...

Hello everybody, hi Evan, this patch changes the lowering of arguments for tail call optimized calls. Before arguments that could be overwritten by each other were explicitly lowered to a stack slot, not giving the register allocator a chance to optimize. Now a sequence of copyto/copyfrom virtual registers ensures that arguments are loaded in (virtual) registers before they are lowered to the

...tting this assertion: >> >> assert(I != VRBaseMap.end() && "Node emitted out of order - late"); >> >> I am not sure why this assertion is being triggered or what I changed > that >> is causing it. >> >> This is asserting when SDValue is FrameIndexSDNode 1. >> >> I don't have any code that modified frameindices until my overloaded >> RegisterInfo function. >> >> I've attached the bc file. If I generate an unoptimized bc file then > there >> is no issue, only when I turn optimizations on do I hit this p...

...of Node needs to be a load, this is the code snippet I used: > > // Now we know which node to spill, perform the spill. > SDValue SpillVal = Node->getOperand(OpNo); > SDValue SpillSlot = CurDAG->CreateStackTemporary(SpillVal.getValueType()); > int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); > SDValue Chain = CurDAG->getStore(CurDAG->getEntryNode(), > SpillVal.getDebugLoc(), > SpillVal, SpillSlot, > MachinePointerInfo::g...

...Node needs to be a load, this is the code > snippet I used: > > // Now we know which node to spill, perform the spill. > SDValue SpillVal = Node->getOperand(OpNo); > SDValue SpillSlot = CurDAG->CreateStackTemporary(SpillVal.getValueType()); > int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); > SDValue Chain = CurDAG->getStore(CurDAG->getEntryNode(), > SpillVal.getDebugLoc(), > SpillVal, SpillSlot, > > MachinePointerIn...